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| small package enhanced flash type 8-bit mcu with eeprom ht66f03/ht66f04 ht68f03/ht68f04 revision: 1.30 date: february 17, 2011
table of contents technical document ...........................................................................7 features ...............................................................................................7 cpu features ........................................................................................................7 peripheral features ................................................................................................7 general description ............................................................................7 selection table ....................................................................................8 block diagram .....................................................................................8 pin assignment ...................................................................................9 pin description ..................................................................................10 ht66f03 ..............................................................................................................10 ht66f04 ..............................................................................................................11 ht68f03/ht68f04 ..............................................................................................12 absolute maximum ratings .............................................................12 d.c. characteristics ..........................................................................13 a.c. characteristics ..........................................................................16 a/d converter characteristics .........................................................17 comparator electrical characteristics ............................................18 power-on reset characteristics ......................................................18 bandgap reference (vbg) characteristic curve ............................19 system architecture .........................................................................20 clocking and pipelining ........................................................................................20 program counter ..................................................................................................21 stack ....................................................................................................................21 arithmetic and logic unit alu ...........................................................................21 flash program memory ....................................................................22 structure ...............................................................................................................22 special vectors .....................................................................................................22 look-up table .......................................................................................................22 table program example .......................................................................................22 in circuit programming .........................................................................................23 ram data memory.............................................................................24 structure ...............................................................................................................24 contents rev. 1.30 2 february 17, 2011 special function register description ...........................................26 indirect addressing registers iar0, iar1 ..........................................................26 memory pointers mp0, mp1 ..............................................................................26 bank pointer bp ................................................................................................27 accumulator acc ..............................................................................................27 program counter low register pcl..................................................................27 look-up table registers tblp, tbhp, tblh .....................................................27 status register status ...................................................................................28 eeprom data memory .....................................................................29 eeprom data memory structure ........................................................................29 eeprom registers ..............................................................................................29 reading data from the eeprom .........................................................................31 writing data to the eeprom ...............................................................................31 write protection ....................................................................................................31 eeprom interrupt ...............................................................................................31 programming considerations ...............................................................................31 oscillator............................................................................................33 oscillator overview ...............................................................................................33 system clock configurations ................................................................................33 external crystal/ ceramic oscillator hxt...........................................................34 external rc oscillator erc ...............................................................................34 internal rc oscillator hirc ...............................................................................34 external 32.768khz crystal oscillator lxt ........................................................35 lxt oscillator low power function ......................................................................35 internal 32khz oscillator lirc ...........................................................................35 operating modes and system clocks .............................................36 system clocks ......................................................................................................36 system operation modes .....................................................................................37 control register ...................................................................................................38 fast wake-up .......................................................................................................39 operating mode switching and wake-up ..............................................................40 normal mode to slow mode switching ...........................................................40 slow mode to normal mode switching ...........................................................41 entering the sleep0 mode ..................................................................................41 entering the sleep1 mode ..................................................................................42 entering the idle0 mode .....................................................................................42 entering the idle1 mode .....................................................................................42 standby current considerations ...........................................................................42 wake-up ...............................................................................................................43 programming considerations ...............................................................................43 contents rev. 1.30 3 february 17, 2011 watchdog timer ................................................................................44 watchdog timer clock source .............................................................................44 watchdog timer control register .........................................................................44 watchdog timer operation ...................................................................................45 reset and initialisation .....................................................................46 reset functions ...................................................................................................46 reset initial conditions .........................................................................................47 input/output ports.............................................................................54 pull-high resistors ................................................................................................54 port a wake-up ....................................................................................................54 i/o port control register ......................................................................................55 pin-remapping functions ......................................................................................55 pin-remapping registers ......................................................................................55 i/o pin structures .................................................................................................56 programming considerations ...............................................................................56 timer modules - tm...........................................................................58 introduction ..........................................................................................................58 tm operation .......................................................................................................59 tm clock source ..................................................................................................59 tm interrupts ........................................................................................................59 tm external pins ..................................................................................................59 programming considerations ...............................................................................60 compact type tm ctm ..................................................................61 compact tm operation ........................................................................................61 compact type tm register description ...............................................................61 compact type tm operating modes ....................................................................65 compare match output mode ..............................................................................65 timer/counter mode .............................................................................................65 pwm output mode ...............................................................................................68 standard type tm stm ..................................................................70 standard tm operation ........................................................................................70 standard type tm register description ...............................................................70 standard type tm operating modes ....................................................................76 compare output mode .........................................................................................76 timer/counter mode .............................................................................................77 pwm output mode ...............................................................................................77 single pulse mode ...............................................................................................79 capture input mode ..............................................................................................81 contents rev. 1.30 4 february 17, 2011 enhanced type tm etm ................................................................81 enhanced tm operation ......................................................................................81 enhanced type tm register description ..............................................................82 enhanced type tm operating modes ..................................................................87 compare output mode .........................................................................................87 timer/counter mode .............................................................................................92 pwm output mode ...............................................................................................92 single pulse output mode ....................................................................................97 capture input mode ..............................................................................................99 analog to digital converter............................................................101 a/d overview .....................................................................................................101 a/d converter register description ....................................................................101 a/d converter data registers adrl, adrh ...................................................101 a/d converter control registers adcr0, adcr1, acerl .............................102 a/d operation .....................................................................................................105 a/d input pins ....................................................................................................106 summary of a/d conversion steps ....................................................................106 programming considerations .............................................................................107 a/d transfer function .........................................................................................107 a/d programming example ................................................................................107 comparators ....................................................................................110 comparator operation ........................................................................................110 comparator interrupt ..........................................................................................110 programming considerations .............................................................................110 interrupts..........................................................................................112 interrupt registers ..............................................................................................112 interrupt operation ..............................................................................................118 external interrupt ................................................................................................122 comparator interrupt ..........................................................................................122 multi-function interrupt ........................................................................................122 a/d converter interrupt .......................................................................................122 time base interrupts ..........................................................................................122 eeprom interrupt .............................................................................................124 lvd interrupt ......................................................................................................124 tm interrupts ......................................................................................................124 interrupt wake-up function ................................................................................124 programming considerations .............................................................................125 contents rev. 1.30 5 february 17, 2011 low voltage detector lvd ...........................................................126 lvd register ......................................................................................................126 lvd operation ....................................................................................................127 configuration options ....................................................................128 application circuits ........................................................................129 ht66f03/ht66f04 ............................................................................................129 ht68f03/ht68f04 ............................................................................................129 instruction set .................................................................................130 introduction .........................................................................................................130 instruction timing ...............................................................................................130 moving and transferring data ............................................................................130 arithmetic operations .........................................................................................130 logical and rotate operations ...........................................................................130 branches and control transfer ...........................................................................130 bit operations .....................................................................................................131 table read operations .......................................................................................131 other operations ................................................................................................131 instruction set summary ....................................................................................131 instruction definition ......................................................................133 package information .......................................................................143 10-pin msop outline dimensions ......................................................................143 16-pin nsop (150mil) outline dimensions .........................................................144 product tape and reel specifications ..........................................145 reel dimensions ................................................................................................145 carrier tape dimensions ....................................................................................146 contents rev. 1.30 6 february 17, 2011 ht66f03/ht66f04/ht68f03/ht68f04 small package enhanced flash type 8-bit mcu with eeprom rev. 1.30 7 february 17, 2011 general description the devices are flash memory type 8-bit high perfor - mance risc architecture microcontrollers. offering us - ers the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d con - verter and a comparator functions. multiple and ex - tremely flexible timer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal watchdog timer, low volt - age reset and low voltage detector coupled with ex - cellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical envi - ronments. a full choice of hxt, lxt, erc, hirc and lirc oscilla - tor functions are provided including a fully integrated system oscillator which requires no external compo - nents for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and mini - mize power consumption. the inclusion of flexible i/o programming features, time-base functions along with many other features en - sure that the devices will find excellent use in applica - tions such as electronic metering, environmental monitoring, handheld instruments, household appli - ances, electronically controlled tools, motor driving in addition to many others. features features cpu features operating voltage: f sys = 8mhz: 2.2v~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 20mhz: 4.5v~5.5v up to 0.2 s instruction cycle with 20mhz system clock at v dd =5v power down and wake-up functions to reduce power consumption five oscillators: external high speed xtal external 32.768khz xtal external rc internal high speed -- no external components internal 32khz -- no external components multi-mode operation: normal, slow, idle and sleep fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 8 subroutine nesting levels bit manipulation instruction peripheral features flash program memory: 1k 14~2k 15 ram data memory: 64 8~96 8 eeprom memory: 64 8 watchdog timer function up to 8 bidirectional i/o lines external interrupt line shared with i/o pin multiple timer module for time measure, input capture, compare match output, pwm output or single pulse output functions comparator function dual time-base functions for generation of fixed time interrupt signals low voltage reset function low voltage detect function multi-channel 12-bit resolution a/d converter package types: 10-pin msop, 16-pin nsop technical document application note ha0075e mcu reset and oscillator circuits application note selection table most features are common to all devices, the main feature distinguishing them are memory capacity, tm features, stack capacity and package types. the following table summarises the main features of each device. part no. vdd program memory data memory data eeprom i/o ext. int. a/d timer module comparator stack package ht66f03 2.2v~ 5.5v 1k 14 64 864 8 8 1 12-bit4 10-bit ctm 1, 10-bit stm 1 14 10msop 16nsop ht66f04 2.2v~ 5.5v 2k 15 96 864 8 8 1 12-bit4 10-bit ctm 1, 10-bit etm 1, 10-bit stm 1 18 10msop 16nsop ht68f03 2.2v~ 5.5v 1k 14 64 864 881 10-bit ctm 1, 10-bit stm 1 14 10msop 16nsop ht68f04 2.2v~ 5.5v 2k 15 96 864 881 10-bit ctm 1, 10-bit stm 1 18 10msop 16nsop block diagram ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 8 february 17, 2011 ! " # $ % & ' ( ) * + ( , * ) * - . / - . / * " ( ' pin assignment note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. 3. vdd&avdd means the vdd and avdd are the double bonding. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 9 february 17, 2011 ) 0 1 2 % 3 ) 1 0 ) & $ 4 3 5 ) 1 & ) % ) 1 % / ) 3 6 ) 1 3 / ( 7 ( ) / ) 8 2 3 % ) 9 4 3 5 & ) : 4 2 3 5 4 % 5 % ) ; 4 1 5 4 2 3 5 4 2 % 5 4 % 5 / * * ( 7 ( ) / * * % 3 ( ( < ( ( ( ( ; ( ( : % & 0 8 9 ) 0 1 2 % 3 ) & $ 4 3 5 ) % ) 3 6 / ) 8 2 3 % ) 9 4 3 5 & ) : 4 2 3 5 4 % 5 % ) ; 4 1 5 4 2 3 5 4 2 % 5 4 % 5 / * * % 3 ( ( < ( ( ( ( ; ( ( : % & 0 8 9 % 3 ( ( < ( ( ( ( ; ( ( : % & 0 8 9 ) 0 1 2 % 4 2 & 5 3 ) 1 0 ) & $ 4 2 & 5 4 3 5 4 & ' 5 ) 1 & ) % 4 & ) 5 ) 1 % / ) 3 4 & ' 5 6 ) 1 3 / ( 7 ( ) / ) 8 2 3 % ) 9 4 2 & 5 4 3 5 & ' & ) : 4 2 3 5 4 % 5 & ) % ) ; 4 1 5 4 2 3 5 4 2 % 5 4 % 5 4 & ) 5 / * * ( 7 ( ) / * * 1 ) 0 1 2 % 4 2 & 5 3 ) 1 0 ) & $ 4 2 & 5 4 3 5 4 & ' 5 ) 1 & ) % 4 & ) 5 ) 1 % / ) 3 4 & ' 5 6 ) 1 3 / ( 7 ( ) / 1 1 1 ) 8 2 3 % ) 9 4 2 & 5 4 3 5 & ' & ) : 4 2 3 5 4 % 5 & ) % ) ; 4 1 5 4 2 3 5 4 2 % 5 4 % 5 4 & ) 5 / * * ( 7 ( ) / * * 1 1 1 ) 0 1 2 % 3 ) 1 0 ) & $ 4 3 5 ) 1 & ) % ) 1 % / ) 3 6 ) 1 3 / ( 7 ( ) / 1 1 1 ) 8 2 3 % ) 9 4 3 5 & ) : 4 2 3 5 4 % 5 % ) ; 4 1 5 4 2 3 5 4 2 % 5 4 % 5 / * * ( 7 ( ) / * * 1 1 % : % 9 % 8 % 0 % & % % % 3 < % & 0 8 9 : ; % : % 9 % 8 % 0 % & % % % 3 < % & 0 8 9 : ; 1 ) 0 1 2 % 3 ) & $ 4 3 5 ) % ) 3 6 / 1 1 1 ) 8 2 3 % ) 9 4 3 5 & ) : 4 2 3 5 4 % 5 % ) ; 4 1 5 4 2 3 5 4 2 % 5 4 % 5 / * * 1 1 % : % 9 % 8 % 0 % & % % % 3 < % & 0 8 9 : ; pin description with the exception of the power pins, all pins on these devices can be referenced by their port name, e.g. pa.0, pa.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, tm pins etc. the function of each pin is listed in the following table, however the de - tails behind how each pin is configured is contained in other sections of the datasheet. the following tables only include the pins which are directly related to the mcu. the pin descriptions of the additional peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional de - scription. ht66f03 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos an0~an3 a/d converter input acerl an pa0~pa3 vref a/d converter reference input adcr1 an pa1 c- comparator input cpc an pa1 c+ comparator input an pa0 cx comparator output cmos pa2 tck0 tm0 input prm st pa4, pa6 or pa7 tck1 tm1 input prm st pa3 or pa7 tp0 tm0 i/o prm st cmos pa3, pa5 or pa2 tp1 tm1 i/o prm st cmos pa4, pa6 or pa7 int external interrupt st pa3 or pa7 osc1 hxt/erc/lxt pin co hxt lxt pa6 osc2 hxt/lxt pin co hxt lxt pa5 res reset pin co st pa7 vdd power supply * pwr avdd a/d converter power supply * pwr vss ground ** pwr avss a/d converter ground ** pwr note: i/t: input type; o/t: output type op: optional by configuration option (co) or register option pwr: power; co: configuration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is the device power supply while avdd is the adc power supply. the avdd pin is bonded together internally with vdd. **: vss is the device ground pin while avss is the adc ground pin. the avss pin is bonded together internally with vss. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 10 february 17, 2011 ht66f04 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos an0~an3 a/d converter input acerl an pa0~pa3 vref a/d converter reference input adcr1 an pa1 c- comparator input cpc an pa1 c+ comparator input an pa0 cx comparator output cmos pa2 tck0 tm0 input prm st pa4, pa6 or pa7 tck1 tm1 input prm st pa3 or pa7 tck2 tm2 input prm st pa3, pa5 or pa2 tp0 tm0 i/o prm st cmos pa3, pa5 or pa2 tp1 tm1 i/o prm st cmos pa4, pa6 or pa7 tp2a tm2 i/o prm st cmos pa6, pa1 or pa7 tp2b tm2 i/o prm st cmos pa5, pa0 or pa2 int external interrupt st pa3 or pa7 osc1 hxt/erc/lxt pin co hxt lxt pa6 osc2 hxt/lxt pin co hxt lxt pa5 res reset pin co st pa7 vdd power supply * pwr avdd a/d converter power supply * pwr vss ground ** pwr avss a/d converter ground ** pwr note: i/t: input type; o/t: output type op: optional by configuration option (co) or register option pwr: power; co: configuration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is the device power supply while avdd is the adc power supply. the avdd pin is bonded together in - ternally with vdd. **: vss is the device ground pin while avss is the adc ground pin. the avss pin is bonded together internally with vss. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 11 february 17, 2011 ht68f03/ht68f04 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos c- comparator input cpc cpc an pa1 c+ comparator input an pa0 cx comparator output cmos pa2 tck0 tm0 input prm st pa4, pa6 or pa7 tck1 tm1 input prm st pa3 or pa7 tp0 tm0 i/o prm st cmos pa3, pa5 or pa2 tp1 tm1 i/o prm st cmos pa4, pa6 or pa7 int external interrupt prm st pa3 or pa7 osc1 hxt/erc/lxt pin co hxt lxt pa6 osc2 hxt/lxt pin co hxt lxt pa5 res reset pin co st pa7 vdd power supply pwr vss ground pwr note: i/t: input type; o/t: output type op: optional by configuration option (co) or register option pwr: power; co: configuration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ................................................................80ma i oh total.............................................................. 80ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 12 february 17, 2011 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hxt, erc, hirc) f sys =8mhz 2.2 5.5 v f sys =12mhz 2.7 5.5 v f sys =20mhz 4.5 5.5 v i dd1 operating current (hxt), (f sys =f h ,f s =f sub =f lirc ) 3v no load, f h =8mhz, adc off, wdt enable 1.0 1.5 ma 5v 2.5 4.0 ma 3v no load, f h =10mhz, adc off, wdt enable 1.2 2.0 ma 5v 2.8 4.5 ma 3v no load, f h =12mhz, adc off, wdt enable 1.5 2.5 ma 5v 3.5 5.5 ma 3v no load, f h =16mhz, adc off, wdt enable 2.0 3.0 ma 5v 4.5 7.0 ma 5v no load, f h =20mhz, adc off, wdt enable 5.5 8.5 ma i dd2 operating current (erc), (f sys =f h ,f s =f sub =f lirc ) 3v no load, f h =6mhz, adc off, wdt enable 0.9 1.5 ma 5v 2.0 3.0 ma 3v no load, f h =8mhz, adc off, wdt enable 1.2 2.0 ma 5v 2.8 4.5 ma 3v no load, f h =12mhz, adc off, wdt enable 1.8 3.0 ma 5v 4.0 6.0 ma 5v no load, f h =16mhz, adc off, wdt enable 5.0 7.5 ma i dd3 operating current (hirc), (f sys =f h ,f s =f sub =f lxr or f lirc ) 3v no load, f h =4mhz, adc off, wdt enable 0.7 1.2 ma 5v 1.5 2.5 ma 3v no load, f h =8mhz, adc off, wdt enable 1.2 2.0 ma 5v 2.8 4.5 ma 3v no load, f h =12mhz, adc off, wdt enable 1.8 3.0 ma 5v 4.0 6.0 ma i dd4 operating current (hxt), (f sys =f l ,f s =f sub =f lirc ) 3v no load, f h =12mhz, f l =f h /2, adc off, wdt enable 0.90 1.50 ma 5v 2.50 3.75 ma 3v no load, f h =12mhz, f l =f h /4, adc off, wdt enable 0.70 1.00 ma 5v 2.00 3.00 ma 3v no load, f h =12mhz, f l =f h /8, adc off, wdt enable 0.60 0.90 ma 5v 1.60 2.40 ma 3v no load, f h =12mhz, f l =f h /16, adc off, wdt enable 0.50 0.75 ma 5v 1.50 2.25 ma 3v no load, f h =12mhz, f l =f h /32, adc off, wdt enable 0.49 0.74 ma 5v 1.45 2.18 ma 3v no load, f h =12mhz, f l =f h /64, adc off, wdt enable 0.47 0.71 ma 5v 1.40 2.10 ma ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 13 february 17, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions i dd5 operating current (lxt), (f sys =f l =f lxt ,f s =f sub =f lxt ) 3v no load, adc off, wdt enable, qosc=0 10 20 a 5v 30 50 a 3v no load, adc off, wdt enable, qosc=1 10 20 a 5v 40 60 a i dd6 operating current (lirc), (f sys =f l =f lirc ,f s =f sub =f lirc ) 3v no load, adc off, wdt enable 10 20 a 5v 30 50 a i dd7 operating current (rtc), (f sys =f l =f lxt ,f s =f sub =f lirc ) 3v no load, adc off, wdt enable, qosc=0 10 20 a 5v 40 60 a i stb1 standby current (idle) (hxt), (f sys =f h ,f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =12mhz 0.6 1.0 ma 5v 1.2 2.0 ma i stb2 standby current (idle) (hxt), (f sys =off, f s =f sys /4) 3v no load, system halt, adc off, wdt enable, f sys =12mhz 1.3 3.0 a 5v 2.2 5.0 a i stb3 standby current (idle) (hxt), (f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =12mhz 1.3 3.0 a 5v 2.2 5.0 a i stb4 standby current (idle) (hxt), (f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =12mhz 1.3 3.0 a 5v 2.2 5.0 a i stb5 standby current (idle) (hxt), (f sys =f l ,f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =12mhz/64 0.6 0.9 ma 5v 1.3 2.0 ma i stb6 standby current (idle) (hxt), (f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =12mhz/64 1.3 3.0 a 5v 2.2 5.0 a i stb7 standby current (idle) (lxt), (f sys =f l =f lxt ,f s =f sub =f lxt ) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 510 a 5v 16 32 a i stb8 standby current (idle) (hxt), (f sys =off, f s =f sys /4) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 510 a 5v 16 32 a i stb9 standby current (idle) (lxt), (f sys =off, f s =f sub =f lxt ) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 510 a 5v 16 32 a i stb10 standby current (idle) (lirc), (f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =32khz 1.3 3.0 a 5v 2.2 5.0 a i stb11 standby current (idle) (lxt), (f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 1.3 3.0 a 5v 2.2 5.0 a i stb12 standby current (sleep) (hxt), (f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt disable, f sys =12mhz 0.1 1.0 a 5v 0.3 2.0 a i stb13 standby current (sleep) (hxt), (f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =12mhz 1.3 5.0 a 5v 2.2 10.0 a i stb14 standby current (sleep) (lxt), (f sys =off, f s =f sub =f lxt or f lirc ) 3v no load, system halt, adc off, wdt disable, f sys =32768hz 0.1 1.0 a 5v 0.3 2.0 a ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 14 february 17, 2011 ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions i stb15 standby current (sleep) (lxt), (f sys =off, f s =f sub =f lxt ) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 510 a 5v 16 32 a v il1 input low voltage for i/o ports, tckx and int 0 0.3v dd v v ih1 input high voltage for i/o ports, tckx and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr1 lvr voltage level lvr enable, 2.10v option 5% 2.10 +5% v v lvr2 lvr enable, 2.55v option 5% 2.55 +5% v v lvr3 lvr enable, 3.15v option 5% 3.15 +5% v v lvr4 lvr enable, 4.20v option 5% 4.20 +5% v v lvd1 lvd voltage level lvden=1, v lvd =2.0v 5% 2.00 +5% v v lvd2 lvden=1, v lvd =2.2v 5% 2.20 +5% v v lvd3 lvden=1, v lvd =2.4v 5% 2.40 +5% v v lvd4 lvden=1, v lvd =2.7v 5% 2.70 +5% v v lvd5 lvden=1, v lvd =3.0v 5% 3.00 +5% v v lvd6 lvden=1, v lvd =3.3v 5% 3.30 +5% v v lvd7 lvden=1, v lvd =3.6v 5% 3.60 +5% v v lvd8 lvden=1, v lvd =4.4v 5% 4.40 +5% v i lvd1 additional power consumption if lvr and lvd is used lvr disable, lvden=1 75 120 a i lvd2 lvr enable, lvden=1 90 150 a v ol output low voltage i/o port 3v i ol =9ma 0.3 v 5v i ol =20ma 0.5 v v oh output high voltage i/o port 3v i oh =3.2ma 2.7 v 5v i oh =7.4ma 4.5 v r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k v 125 1.25v reference with buffer voltage 3% 1.25 +3% v i 125 additional power consumption if 1.25v reference with buffer is used 200 300 a ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 15 february 17, 2011 ta=25 c a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operating clock 2.2v~5.5v dc 8 mhz 2.7v~5.5v dc 12 mhz 4.5v~5.5v dc 20 mhz f sys system clock (hxt) 2.2v~5.5v 0.4 8 mhz 2.7v~5.5v 0.4 12 mhz 4.5v~5.5v 0.4 20 mhz f erc system clock (erc) 5v ta=25 c, r=120k * 2% 8 +2% mhz 5v ta=0~70 c, r=120k * 5% 8 +6% mhz 5v ta= 40c~85c, r=120k * 7% 8 +9% mhz 3.0v~ 5.5v ta= 40c~85c, r=120k * 9% 8 +10% mhz 2.2v~ 5.5v ta= 40c~85c, r=120k * 15% 8 +10% mhz f hirc system clock (hirc) 3v/5v ta=25c 2% 4 +2% mhz 3v/5v ta=25c 2% 8 +2% mhz 5v ta=25c 2% 12 +2% mhz 3v/5v ta=0~70c 5% 4 +5% mhz 3v/5v ta=0~70c 5% 8 +4% mhz 5v ta=0~70c 5% 12 +3% mhz 2.2v~ 3.6v ta=0~70c 7% 4 +7% mhz 3.0v~ 5.5v ta=0~70c 5% 4 +9% mhz 2.2v~ 3.6v ta=0~70c 6% 8 +4% mhz 3.0v~ 5.5v ta=0~70c 4% 8 +9% mhz 3.0v~ 5.5v ta=0~70c 6% 12 +7% mhz 2.2v~ 3.6v ta= 40c~85c 12% 4 +8% mhz 3.0v~ 5.5v ta= 40 c~85c 10% 4 +9% mhz 2.2v~ 3.6v ta= 40c~85c 15% 8 +5% mhz 3.0v~ 5.5v ta= 40c~85c 8% 8 +9% mhz 3.0v~ 5.5v ta= 40c~85c 12% 12 +7% mhz f lxt system clock (lxt) 32768 hz ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 16 february 17, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions f timer timer i/p frequency (tmr) 2.2~ 5.5v 2 8 mhz 2.7~ 5.5v 2 10 mhz 3.3~ 5.5v 2 12 mhz 4.5~ 5.5v 2 16 mhz f lirc system clock (lirc) 5v ta=25c 10% 32 +10% khz t res external reset low pulse width 1 s t int interrupt pulse width 1 t sys t lvr low voltage width to reset 120 240 480 s t lvd low voltage width to interrupt 20 45 90 s t lvds lvdo stable time 15 s t bgs vbg turn on stable time 200 s t sst system start-up timer period (wake-up from halt) f sys =xtal or rtc osc 1024 t sys f sys =erc or hirc osc 15~16 f sys =lirc osc 1~2 note: 1. t sys =1/f sys 2. * for f erc , as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1 f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. a/d converter characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d converter operating voltage v ref =av dd 2.7 5.5 v v adi a/d converter input voltage 0 vref v v ref a/d converter reference voltage 2 av dd v dnl differential non-linearity 5v t adck = 1.0 s 1 2 lsb inl integral non-linearity 5v t adck = 1.0 s 2 4 lsb i adc additional power consumption if a/d converter is used 3v no load, t adck = 0.5 s 0.90 1.35 ma 5v no load, t adck = 0.5 s 1.20 1.80 ma t adck a/d converter clock period 2.2~ 5.5v 0.5 10 s t adc a/d conversion time (include sample and hold time) 2.2~ 5.5v 12-bit a/d converter 16 t adck t ads a/d converter sampling time 2.2~ 5.5v 4 t adck t on2st a/d converter on-to-start time 2.2~ 5.5v 2 s ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 17 february 17, 2011 ta=25 c comparator electrical characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v cmp comparator operating voltage 2.2 5.5 v i cmp comparator operating current 3v 37 56 a 5v 130 200 a v cmpos comparator input offset voltage 10 10 mv v hys hysteresis width 20 40 60 mv v cm comparator common mode voltage range v ss v dd 1.4v v a ol comparator open loop gain 60 80 db t pd comparator response time with 100mv overdrive (note) 370 560 ns note: measured with comparator one input pin at v cm =(v dd 1.4)/2 while the other pin input transition from v ss to (v cm +100mv) or from v dd to (v cm -100mv). power-on reset characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv r por ac vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 18 february 17, 2011 / * * / / * * bandgap reference (vbg) characteristic curve ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 19 february 17, 2011 % = & % 9 % = & & 3 % = & & 9 % = & 0 3 % = & 0 9 % = & 8 3 % = & 8 9 % = & 9 3 % = & 9 9 % = & : 3 % = & : 9 % = & ; 3 & = ; / 0 = % 9 / 9 = : / & 9 8 9 < 3 " ( / ' > " ( / ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 20 february 17, 2011 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their in - ternal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, in - crement, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accu - mulator and the alu. certain internal registers are im - plemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o and a/d control sys - tem with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc, lirc or erc oscillator is subdivided into four in- ternally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. ( = ( ? @ # ( = ( ? % @ ( = ( ? 6 % @ # ( = ( ? @ ( = ( ? 6 & @ # ( = ( ? 6 % @ 6 % 6 & a b ? ( , @ ( , ( % ( ( , ( & ( , ( 0 ( , ( 8 " system clocking and pipelining ( = ( % # ( = ( % ( = ( & ( " % & 0 8 9 : * - ) b c / ( ) d 4 % & e 5 ) - - ( * - ) b - ( 4 % & e 5 c c 1 # ( = ( & ( = ( 0 ( = ( : # ( = ( : ( = ( ; instruction fetching ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 21 february 17, 2011 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low regis - ter, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. device program counter program counter high byte pcl register ht66f03 ht68f03 pc9, pc8 pcl7~pcl0 ht66f04 ht68f04 pc10~pc8 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short pro- gram jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 loca - tions. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manip - ulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the acti - vated level is indexed by the stack pointer, and is nei - ther readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the pro - gram counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is re - stored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overflow, the first program counter save in the stack will be lost. device stack levels ht66f03/ht68f03 4 ht66f04/ht68f04 8 arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic oper- ations of the instruction set. connected to the main microcontroller data bus, the alu receives related in- struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti ( , ( - + ( % , ( - + ( & , ( - + ( 0 , ( - + ( 1 " ( a ( , , ' ( a ( , ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 22 february 17, 2011 flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifi - cation on the same device. by using the appropriate programming tools, these flash devices offer users the flexibility to conveniently debug and develop their appli - cations while also offering a means of field programming and updating. structure the program memory has a capacity of 1k 14 bits to 2k 15 bits. the program memory is addressed by the program counter and also contains data, table informa - tion and interrupt entries. table data, which can be setup in any location within the program memory, is ad - dressed by a separate table pointer register. device capacity ht66f03 ht68f03 1k14 ht66f04 ht68f04 2k15 special vectors within the program memory, certain locations are re - served for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialis - ation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers define the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] instructions, respec - tively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as speci - fied in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this trans - ferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data flow of the look-up table. table program example the following example shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data lo- cated in the program memory which is stored there us- ing the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an ini- tial value of 06h . this will ensure that the first data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is refer - enced to the first address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. " / 3 3 3 8 e 3 0 e % 8 ( 3 3 & 3 e " / % 9 ( 3 ; e 3 3 3 3 e program memory structure ( ' - e ! ( e ( ' - . ( ' ' - ( * ) % 8 f % 9 ( - ( " ( ' e ( ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 23 february 17, 2011 in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit us - ing a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards com - plete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufac - turers to easily keep their manufactured products sup - plied with the latest program releases without removal and re-insertion of the device. mcu programming pins function pa0 serial data input/output pa2 serial clock res device reset vdd power supply vss ground the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two ad - ditional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supple - mentary literature. during the programming process the res pin will be held low by the programmer disabling the normal opera - tion of the microcontroller and taking control of the pa0 and pa2 i/o pins for data and clock programming pur - poses. the user must there take care to ensure that no other outputs are connected to these two pins. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address mov tblp,a ; is referenced mov a,07h ; initialise high table pointer tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 705h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 24 february 17, 2011 programmer pin mcu pins res pa7 data pa0 clk pa2 programmer and mcu pins ram data memory the data memory is a volatile area of 8-bit wide ram in- ternal memory and is the location where temporary in- formation is stored. structure divided into two sections, the first of these is an area of ram, known as the special function data memory. here are located registers which are necessary for cor - rect operation of the device. many of these registers can be read from and written to directly under program con - trol, however, some remain protected from user manipu - lation. device capacity bank 0 bank 1 ht66f03 ht68f03 648 40h~7fh 40h (eec) available only ht66f04 ht68f04 968 40h~9fh 40h (eec) available only the second area of data memory is known as the gen - eral purpose data memory, which is reserved for gen - eral purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks for all the devices. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only acces - sible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data mem - ory for all devices is the address 00h. g g g h / * * * ) ) - 2 h / ( ( * ) ) - 2 / / * * ( ! ( note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. 3 3 e 3 % e 3 & e 3 0 e 3 8 e 3 9 e 3 : e 3 ; e 3 e 3 < e 3 ) e 3 ' e 3 e 3 * e 3 e 3 e % 3 e % % e % & e % 0 e % 8 e % 9 e % : e % ; e % e % < e % ) e % ' e % e % * e % e % e ) 3 3 ) % % ' ) - ' - ' - e ' e ) ! * - / * 1 > 1 3 1 % 1 & 3 ! & ) ) ) ! ) 2 ! ! * ' ! ! ) * & 3 e & % e & & e & 0 e & 8 e & 9 e & : e & ; e & e & < e & ) e & ' e & e & * e & e & e 0 3 e 0 % e 0 & e 0 0 e 0 8 e 0 9 e 0 : e 0 ; e 0 e 0 < e 0 ) e 0 ' e 0 e 0 * e 0 e 0 e ) * - ) * e ) * 3 ) * % ) - ! ! 3 3 3 % 3 * - 3 * e 3 ) - 3 ) e % 3 % % % * - % * e % ) - % ) e ! ! ! ! ! ! ! ! ! ! ! ! ht66f03 special purpose data memory ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 25 february 17, 2011 3 3 e 3 % e 3 & e 3 0 e 3 8 e 3 9 e 3 : e 3 ; e 3 e 3 < e 3 ) e 3 ' e 3 e 3 * e 3 e 3 e % 3 e % % e % & e % 0 e % 8 e % 9 e % : e % ; e % e % < e % ) e % ' e % e % * e % e % e ) 3 3 ) % % ' ) - ' - ' - e ' e ) ! * - / * 1 > 1 3 1 % 1 & 3 % & ) ) ) ! ) 2 ! ! * ' ! ! ) * & 3 e & % e & & e & 0 e & 8 e & 9 e & : e & ; e & e & < e & ) e & ' e & e & * e & e & e 0 3 e 0 % e 0 & e 0 0 e 0 8 e 0 9 e 0 : e 0 ; e 0 e 0 < e 0 ) e 0 ' e 0 e 0 * e 0 e 0 e ) * - ) * e ) * 3 ) * % ) - ! ! 3 3 3 % 3 * - 3 * e 3 ) - 3 ) e % 3 % % % * - % * e % ) - % ) e & 3 & % & & & * - & * e & ) - & ) e & ' - & ' e ! ! ! ht66f04 special purpose data memory 3 3 e 3 % e 3 & e 3 0 e 3 8 e 3 9 e 3 : e 3 ; e 3 e 3 < e 3 ) e 3 ' e 3 e 3 * e 3 e 3 e % 3 e % % e % & e % 0 e % 8 e % 9 e % : e % ; e % e % < e % ) e % ' e % e % * e % e % e ) 3 3 ) % % ' ) - ' - ' - e ' e ) ! * - / * 1 > 1 3 1 % 1 & 3 ! & ) ) ) ! ) 2 ! ! * ' ! ! ) * & 3 e & % e & & e & 0 e & 8 e & 9 e & : e & ; e & e & < e & ) e & ' e & e & * e & e & e 0 3 e 0 % e 0 & e 0 0 e 0 8 e 0 9 e 0 : e 0 ; e 0 e 0 < e 0 ) e 0 ' e 0 e 0 * e 0 e 0 e ! ! ! ! ! ! ! 3 3 3 % 3 * - 3 * e 3 ) - 3 ) e % 3 % % % * - % * e % ) - % ) e ! ! ! ! ! ! ! ! ! ! ! ! ht68f03/ht68f04 special purpose data memory > " * ( 8 3 e ; e ! > " * ( 8 3 e < e ! general purpose data memory ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 26 february 17, 2011 special function register description most of the special function register details will be de - scribed in the relevant functional section, however sev - eral registers require a separate description in this section. indirect addressing registers iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad - dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect ad - dressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no op - eration. memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are pro - vided. these memory pointers are physically imple - mented in the data memory and can be manipulated in the same way as normal registers providing a conve - nient way with which to address and track data. when any operation to the relevant indirect addressing regis - ters is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct ad - dressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. note that for this series of devices, the memory pointers, mp0 and mp1, are both 8-bit registers and used to ac - cess the data memory together with their corresponding indirect addressing registers iar0 and iar1. the following example shows how to clear a section of four data memory locations already defined as loca - tions adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 27 february 17, 2011 bank pointer bp for this series of devices, the data memory is divided into two banks. selecting the required data memory area is achieved using the bank pointer. bit 0 is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being ac - cessed irrespective of the value of the bank pointer. ac - cessing data from banks other than bank 0 must be implemented using indirect addressing. accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tbhp, tblh these three special function registers are used to con - trol operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is lo - cated. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, al - lowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been exe - cuted. note that the lower order table data byte is trans - ferred to a user defined location. bank pointer register bit76543210 name dmbp0 r/w r/w 0 bit7~1 unimplemented, read as 0 bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 28 february 17, 2011 status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib - ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high - est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit76543210 name to ov z ac c r/w r r r/w r/w r/w r/w 00xxxx x unknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out flag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down flag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 29 february 17, 2011 eeprom data memory the device contains an area of internal eeprom data memory. eeprom, which stands for electrically eras - able programmable read only memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows in - formation such as product identification numbers, cali - bration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64 8 bits for this series of devices. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an ad - dress and data register in bank 0 and a single control register in bank 1. device capacity address all devices 648 00h ~ 3fh eeprom registers three registers control the overall operation of the inter - nal eeprom data memory. these are the address reg - ister, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in bank1, cannot be addressed directly and can only be read from or writ - ten to indirectly using the mp1 memory pointer and indi - rect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must first be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are exe - cuted. eeprom register list name bit 76543210 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rd eea register bit76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w xxxxxx x unknown bit7~6 unimplemented, read as 0 bit5~0 data eeprom address data eeprom address bit 5 ~ bit 0 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 30 february 17, 2011 eec register bit76543210 name wren wr rd r/w r/w r/w r/w r/w 0000 bit7~4 unimplemented, read as 0 bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has finished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has finished. setting this bit high will have no effect if the wren has not first been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has finished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has finished. setting this bit high will have no effect if the rden has not first been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. eed register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w xxxxxxxx x unknown bit7~0 data eeprom address data eeprom address bit 7 ~ bit 0 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 31 february 17, 2011 reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must first be set high to en - able the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initi - ate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be auto - matically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is exe - cuted. the application program can poll the rd bit to de - termine when the data is valid for reading. writing data to the eeprom to write data to the eeprom, the write enable bit, wren, in the eec register must first be set high to en - able the write function. the eeprom address of the data to be written must then be placed in the eea regis - ter and the data placed in the eed register. if the wr bit in the eec register is now set high, an internal write cy - cle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has finished can be im- plemented either by polling the wr bit in the eec regis- ter or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the ap- plication program can therefore poll the wr bit to deter - mine when the write cycle has ended. write protection protection against inadvertent write operation is pro - vided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write opera - tions. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write or read interrupt is generated when an eeprom write or read cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function inter - rupt request flag will both be set. if the global, eeprom and multi-function interrupts are enabled and the stack is not full, a jump to the associated multi-function inter - rupt vector will take place. when the interrupt is serviced only the multi-function interrupt flag will be automatically reset, the eeprom interrupt flag must be manually re- set by the application program. more details can be ob- tained in the interrupt section. programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensur- ing that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be nor - mally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. al - though certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 32 february 17, 2011 programming examples reading data from the eeprom - polling method mov a, eeprom_adres ; user defined address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eed ; move read data to register mov read_data, a writing data to the eeprom polling method mov a, eeprom_adres ; user defined address mov eea, a mov a, eeprom_data ; user defined data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 33 february 17, 2011 oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of configuration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watch - dog timer and time base interrupts. external oscilla - tors requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power re - quirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dy - namically switching between fast and slow system clock, the device has the flexibility to optimize the perfor - mance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins external crystal hxt 400khz~ 20mhz osc1/ osc2 external rc erc 8mhz osc1 internal high speed rc hirc 4, 8 or 12mhz external low speed crystal lxt 32.768khz osc1/ osc2 internal low speed rc lirc 32khz oscillator types system clock configurations there are four methods of generating the system clock, three high speed oscillators and two low speed oscilla - tors. the high speed oscillators are the external crystal/ ceramic oscillator, external rc network oscillator and the internal 4mhz, 8mhz or 12mhz rc oscillator. the two low speed oscillators are the internal 32khz rc os - cillator and the external 32.768khz crystal oscillator. se - lecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. hxt high speed oscillators erc hirc lirc low speed oscillators f h 6-stage prescaler high/low speed oscillator configuration options hlclk, cks2~cks0 bits f h /2 f h /4 f h /8 f h /16 f h /32 f h /64 f l fast wake-up from sleep mode or idle mode control (for hxt only) f sys lxt f sub system clock configurations ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 34 february 17, 2011 the actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. the osc1 and osc2 pins are used to connect the external components for the ex - ternal crystal, external rc and external low speed crys - tal oscillators. once the osc1 or both osc1 and osc2 pins are used for erc or hxt oscillators, the corre - sponding low speed oscillator must be the internal low speed rc oscillator lirc. therefore there are some limitations to select the high speed and low speed oscil - lators for the high and low speed system clock sources. the available selections for high speed and low speed oscillators are shown in the following table. oscillator types available oscillator selections 1234 high speed oscillator hxt erc hirc hirc low speed oscillator lirc lirc lirc lxt external crystal/ ceramic oscillator hxt the external crystal/ ceramic system oscillator is one of the high frequency oscillator choices, which is se- lected via configuration option. for most crystal oscilla- tor configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requir- ing external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be neces - sary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. crystal oscillator c1 and c2 values crystal frequency c1 c2 20mhz 6pf 8pf 16mhz 6pf 8pf 12mhz 8pf 10pf 8mhz 8pf 10pf 4mhz 8pf 10pf 1mhz 100pf 100pf note: c1 and c2 values are for guidance only. crystal recommended capacitor values external rc oscillator erc using the erc oscillator only requires that a resistor, with a value between 56k and 2.4m , is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscilla - tor configuration. it is only the external resistor that de - termines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to en - sure that the influence of the power supply voltage, tem - perature and process variations on the oscillation frequency are minimised. as a resistance/frequency ref- erence point, it can be noted that with an external 120k resistor connected and with a 5v voltage power supply and temperature of 25 c degrees, the oscillator will have a frequency of 8mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pa6, leaving pin pa5 free for use as a normal i/o pin. internal rc oscillator hirc the internal rc oscillator is a fully integrated system os - cillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal fre - quency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fixed oscillation fre - quency of the high speed internal 8mhz rc oscillator will have a tolerance within 2%. note that if this internal external rc oscillator erc ! " # # " # $ % & % % ' ( % ) # crystal/resonator oscillator hxt ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 35 february 17, 2011 system clock option is selected as the high speed oscil - lator, as it requires no external pins for its operation, and the lirc oscillator is selected as the low speed oscilla - tor, i/o pins pa6 and pa5 can only be used as normal i/o pins. if the low speed oscillator is lxt oscillator rather than the lirc oscillator, the i/o pins pa6 and pa5 are used as the external 32.768khz crystal oscilla - tor (lxt) pins. external 32.768khz crystal oscillator lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is se - lected via configuration option. this clock source has a fixed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins osc1 and osc2. the external resistor and capacitor components con - nected to the 32.768khz crystal are necessary to pro - vide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to dif - ferent crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. how- ever, in many microcontroller applications it may be nec- essary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the ex - act values of c1 and c2 should be selected in consulta - tion with the crystal or resonator manufacturer s specification. the external parallel feedback resistor, rp, is required. some configuration options determine if the osc1 and osc2 pins are used for the lxt oscillator or as i/o pins. if the lxt oscillator is not used for any clock source, the osc1 and osc2 pins can be used as normal i/o pins. if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the osc1 and osc2 pins. lxt oscillator c1 and c2 values crystal frequency c1 c2 32.768khz 10pf 10pf note: 1. c1 and c2 values are for guidance only. 2. r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode se - lection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 quick start 1 low-power after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. how - ever, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the appli- cation program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always func- tion normally, the only difference is that it will take more time to start up if in the low-power mode. internal 32khz oscillator lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via config - uration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming dur - ing the manufacturing process and the inclusion of inter - nal frequency compensation circuits are used to ensure that the influence of the power supply voltage, tempera - ture and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fixed oscillation fre - quency of 32khz will have a tolerance within 10%. supplementary oscillators the low speed oscillators, in addition to providing a sys - tem clock source are also used to provide a clock source to two other device functions. these are the watchdog timer and the time base interrupts. * # " # $ % & % % ' % ) # + , - . / 0 external lxt oscillator ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 36 february 17, 2011 operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in bat - tery powered portable applications. the fast clocks re - quired for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best perfor - mance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using config - uration options and register programming, a clock sys - tem can be configured to obtain maximum application performance. the main system clock, can come from either a high fre - quency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either an hxt, erc or hirc oscillator, selected via a configuration option. the low speed system clock source can be sourced from internal clock f l .iff l is se - lected then it can be sourced by either the lxt or lirc oscillators, selected via a configuration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the periph - eral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks are sourced by either the lxt or lirc oscillators, selected via configuration options. the f sub clock is used to pro - vide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. hxt high speed oscillators erc hirc lirc low speed oscillators f h 6-stage prescaler high/low speed oscillator configuration options hlclk, cks2~cks0 bits f h /2 f h /4 f h /8 f h /16 f h /32 f h /64 f l fast wake-up from sleep mode or idle mode control (for hxt only) f sys lxt f s configuration option f sys /4 f sub wdt f s f sys /4 time base f tb tbck f tbc system clock configurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 37 february 17, 2011 together with f sys /4 it is also used as one of the clock sources for the watchdog timer. the f tbc clock is used as a source for the time base interrupt functions and for the tms. system operation modes there are six different modes of operation for the microcontroller, each one with its own special character - istics and which can be chosen according to the specific performance and power requirements of the applica - tion. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f sub f s f tbc normal mode on f h ~f h /64 on on on slow mode on f l on on on idle0 mode off off on on/off on idle1 mode off on on on on sleep0 mode off off off off off sleep1 mode off off on on off normal mode as the name suggests this is one of the main operat - ing modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt, erc or hirc oscillators. the high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~lcks0 and hlclk bits in the smod register. although a high speed os- cillator is used, running the microcontroller at a di- vided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller oper - ates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an halt instruc - tion is executed and when the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to 0 . if the lvden is set to 1 ,itwon t enter the sleep0 mode. sleep1 mode the sleep mode is entered when an halt instruc - tion is executed and when the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the lvden is 1 or the watchdog timer function is enabled and if its clock source is chosen via configuration option to come from the f sub . idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod reg- ister is high and the fsyson bit in the wdtc register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watch- dog timer and tms. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the watchdog timer clock, f s , will either be on or off de - pending upon the f s clock source. if the source is f sys /4 then the f s clock will be off, and if the source co - mes from f sub then f s will be on. idle1 mode the idle1 mode is entered when a halt instruction is executed and when the idlen bit in the smod reg - ister is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral func - tions operational such as the watchdog timer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the watchdog timer clock, f s , will be on. if the source is f sys /4 then the f s clock will be on, and if the source comes from f sub then f s will be on. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 38 february 17, 2011 control register a single register, smod, is used for overall control of the internal clocks within the device. smod register b i t76543210 name cks2 cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 00000011 bit 7~5 cks2~cks0 : the system clock selection when hlclk is 0 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f sub clock source is initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available. bit 3 lto : low speed system oscillator ready flag 0: not ready 1: ready this is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the flag will be low when in the sleep0 mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready flag 0: not ready 1: ready this is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. this flag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this flag will always be read as 1 by the application program after device power-on. the flag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 39 february 17, 2011 fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a tem - porary clock to first drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast wake-up function has no effect because the f sub clock is stopped. the fast wake-up enable/dis - able function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the normal mode system clock, and if the fast wake-up function is en - abled, then it will take one to two t sub clock cycles of the lirc oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto flag will switch high and the system will switch over to operating from the hxt oscillator. if the erc or hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cy - cles of the erc or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 1024 hxt cycles 1024 hxt cycles 1~2 hxt cycles 1 1024 hxt cycles 1~2 f sub cycles (system runs with f sub first for 1024 hxt cycles and then switches over to run with the hxt clock) 1~2 hxt cycles erc x 15~16 erc cycles 15~16 erc cycles 1~2 erc cycles hirc x 15~16 hirc cycles 15~16 hirc cycles 1~2 hirc cycles lirc x 1~2 lirc cycles 1~2 lirc cycles 1~2 lirc cycles lxt x 1024 lxt cycles 1024 lxt cycles 1~2 lxt cycles wake-up times note that if the watchdog timer is disabled, which means that the lxt and lirc are all both off, then there will be no fast wake-up function available when the device wakes-up from the sleep0 mode. / $ 1 2 # 3 4 5 6 1 7 8 9 5 9 : ; 1 3 8 / < / ( , / 4 5 3 9 5 9 / $ 1 2 # 4 5 6 1 7 8 3 8 3 9 5 9 / $ 1 2 # 4 5 6 1 7 8 3 8 3 9 5 9 3 8 1 1 4 5 3 9 5 9 / / $ 1 2 # 3 4 5 6 1 7 8 9 5 9 : 1 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 40 february 17, 2011 operating mode switching and wake-up the device can switch between operating modes dy - namically allowing the user to select the best perfor - mance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruc - tion. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is de - termined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which im - plies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l .if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the op - eration of other internal functions such as the tms. the accompanying flowchart shows what happens when the device moves between the various operating modes. normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by setting the hlclk bit to 0 and setting the cks2~cks0 bits to 000 or 001 in the smod register. this will then use the low speed system oscilla - tor which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power con - sumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is moni - tored using the lto bit in the smod register. 1 : = # 1 7 7 4 = # 1 7 7 4 = # 6 7 1 = # 6 1 7 = # = $ 1 = # > < > 8 2 9 ; / 1 1 > 8 : # 1 6 1 7 8 / $ 1 2 # : 1 6 1 7 8 / $ 1 2 # 6 1 7 8 * 3 8 / $ 1 2 # 6 1 7 8 * 3 8 / $ 1 2 # ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 41 february 17, 2011 = $ 1 = # 1 7 7 4 = # 1 7 7 4 = # 6 1 7 = # 6 1 7 = # 1 : = # > < > 9 * 9 / 1 1 > 8 / 1 1 > 8 : # 1 6 1 7 8 / $ 1 2 # : 1 6 1 7 8 / $ 1 2 # 6 1 7 8 * 3 8 / $ 1 2 # 6 1 7 8 * 3 8 / $ 1 2 # slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0 , but cks2~cks0 is set to 010, 011, 100, 101, 110 or 111 . as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the halt instruc- tion in the application program with the idlen bit in smod register equal to 0 and the wdt and lvd both off. when this instruction is executed under the condi - tions described above, the following will occur: the system clock, wdt clock and time base clock will be stopped and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 42 february 17, 2011 entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: the system clock and time base clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in wdtc register equal to 0 . when this instruction is executed under the condi- tions described above, the following will occur: the system clock will be stopped and the application program will stop at the halt instruction, but the time base clock and f sub clock will be on. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in wdtc register equal to 1 . when this instruction is executed under the with conditions described above, the following will occur: the system clock and time base clock and f sub clock will be on and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt is enabled regardless of the wdt clock source which originates from the f sub clock or from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are con - nected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum cur - rent is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the sys - tem oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 43 february 17, 2011 wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as fol - lows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup using the pawu regis - ter to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the pro - gram will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fi- nally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular inter - rupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the high speed and low speed oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hirc and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hirc oscillator has finished its sst period. if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute first in - struction after hto is 1 . at this time, the lxt oscilla - tor may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the first instruction is executed. if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1 , the system clock can be switched to the lirc oscillator after wake up. there are peripheral functions, such as wdt and tms, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change ac - cordingly. the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub . ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 44 february 17, 2011 watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the in - ternal clock, f s , which is in turn supplied by one of two sources selected by configuration option: f sub or f sys /4. the f sub clock can be sourced from either the lxt or lirc oscillators, again chosen via a configuration op - tion. the watchdog timer source clock is then subdi - vided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specified internal clock period can vary with vdd, temperature and pro - cess variations. the lxt oscillator is supplied by an ex - ternal 32.768khz crystal. the other watchdog timer clock source option is the f sys /4 clock. the watchdog timer clock source can originate from its own internal lirc oscillator, the lxt oscillator or f sys /4. it is divided by a value of 2 8 to 2 15 , using the ws2~ws0 bits in the wdtc register to obtain the required watchdog timer time-out period. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. this reg - ister together with several configuration options control the overall operation of the watchdog timer. wdtc register bit76543210 name fsyson ws2 ws1 ws0 wdten3 wdten2 wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por01111010 bit 7 fsyson: f sys control in idle mode 0: disable 1: enable bit6~4 ws2, ws1, ws0 : wdt time-out period selection 000: 256/f s 001: 512/f s 010: 1024/f s 011: 2048/f s 100: 4096/f s 101: 8192/f s 110: 16384/f s 111: 32768/f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period. bit3~0 wdten3, wdten2, wdten1, wdten0 : wdt software control 1010: disable other: enable ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 45 february 17, 2011 - ? & ) # : ? @ - ( < a ( b ( - : 4 - ? ? = 5 c : ! & 1 : & 1 : & 6 1 : < : @ ( - < ( a b = 5 c 5 9 3 ( & watchdog timer watchdog timer operation the watchdog timer operates by providing a device re - set when its timer overflows. this means that in the ap - plication program and during normal operation the user has to strategically clear the watchdog timer before it overflows to prevent the watchdog timer from execut - ing a reset. this is done using the clear watchdog in - structions. if the program malfunctions for whatever reason, jumps to an unkown location, or enters an end - less loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overflow and reset the device. some of the watch - dog timer options, such as enable/disable, clock source selection and clear instruction type are selected using configuration options. in addition to a configuration op - tion to enable/disable the watchdog timer, there are also four bits, wdten3~wdten0, in the wdtc regis - ter to offer an additional enable/disable control of the watchdog timer. to disable the watchdog timer, as well as the configuration option being set to disable, the wdten3~wdten0 bits must also be set to a specific value of 1010 . any other values for these bits will keep the watchdog timer enabled, irrespective of the configu - ration enable/disable setting. after power on these bits will have the value of 1010. if the watchdog timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. note that if the watchdog timer has been disabled, then any instruction relating to its operation will result in no operation. wdt configuration option wdten3~ wdten0 bits wdt wdt enable xxxx enable wdt disable except 1010 enable wdt disable 1010 disable watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog timer software clear instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed alter - nately to successfully clear the watchdog timer. note that for this second option, if clr wdt1 is used to clear the watchdog timer, successive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the watchdog timer. similarly after the clr wdt2 instruction has been ex - ecuted, only a successive clr wdt1 instruction can clear the watchdog timer. the maximum time out period is when the 2 15 division ra- tio is selected. as an example, with a 32.768khz lxt oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. if the f sys /4 clock is used as the watchdog timer clock source, it should be noted that when the system enters the sleep or idle0 mode, then the instruction clock is stopped and the watchdog timer may lose its protecting purposes. for systems that operate in noisy environments, using the f sub clock source is strongly recommended. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 46 february 17, 2011 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer over- flows and resets the microcontroller . all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller . as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. res pin as the reset pin is shared with pa.7, the reset function must be selected using a configuration option. al - though the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir - cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. 4 $ ( 7 < . < . d d - d + d note: * it is recommended that this component is added for added esd protection ** it is recommended that this component is added in environments where power line noise is significant external res circuit 7 6 e f f note: t rstd is power-on delay, typical time=100ms power-on reset timing chart ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 47 february 17, 2011 pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the bat - tery, the lvr will automatically reset the device inter - nally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ig - nore it and will not perform a reset function. one of a range of specified voltage values for v lvr can be se - lected using configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera- tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1. watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset uu res or lvr reset during normal or slow mode operation 1u wdt time-out reset during normal or slow mode operation 11 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer modules timer counter will be turned off input/output ports i/o ports will be setup as inputs, and an0~an3 as a/d input pins stack pointer stack pointer will point to the top of the stack f : ? 6 note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart : ? 6 wdt time-out reset during sleep or idle timing chart 1 6 f note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart 7 6 e f note: t rstd is power-on delay, typical time=100ms res reset timing chart ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 48 february 17, 2011 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. ht66f03 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 0 0 0 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xx xxxx uu uuuu uu uuuu uu uuuu tbhp xx uu uu uu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 00 00 00 uu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0 0 0 0 0 0 u u mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi2 00 00 00 00 00 00 uu uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu prm 0101 0000 0101 0000 0101 0000 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu eea xx xxxx xx xxxx xx xxxx uu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu adrl (adrfs=0) xxxx xxxx xxxx uuuu adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=1) xxxx xxxx xxxx uuuu adcr0 0110 00 0110 00 0110 00 uuuu uu adcr1 00 0 000 00 0 000 00 0 000 uu u uuu acerl 1111 1111 1111 uuuu ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 49 february 17, 2011 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) cpc 1000 0 1 1000 0 1 1000 0 1 uuuu uu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu note: u stands for unchanged x stands for unknown stands for unimplemented ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 50 february 17, 2011 ht66f04 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 0 0 0 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu tbhp xxx uuu uuu uuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 00 00 00 uu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0 0 0 0 0 0 u u mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 000 0000 000 0000 000 0000 uuu uuuu mfi2 00 00 00 00 00 00 uu uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu prm 0101 0000 0101 0000 0101 0000 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu eea xx xxxx xx xxxx xx xxxx uu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu adrl (adrfs=0) xxxx xxxx xxxx uuuu adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=1) xxxx xxxx xxxx uuuu adcr0 0110 00 0110 00 0110 00 uuuu uu adcr1 00 0 000 00 0 000 00 0 000 uu u uuu acerl 1111 1111 1111 uuuu cpc 1000 0 1 1000 0 1 1000 0 1 uuuu uu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 51 february 17, 2011 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu tm2c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dh 00 00 00 uu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 00 00 00 uu tm2bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2bh 00 00 00 uu note: u stands for unchanged x stands for unknown stands for unimplemented ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 52 february 17, 2011 ht68f03 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 0 0 0 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xx xxxx uu uuuu uu uuuu uu uuuu tbhp xx uu uu uu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 00 00 00 uu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0 00 0 00 0 00 0 00 0 00 0 00 u uu u uu intc2 0 0 0 0 0 0 u u mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi2 00 00 00 00 00 00 uu uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu prm 0101 0000 0101 0000 0101 0000 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu eea xx xxxx xx xxxx xx xxxx uu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu cpc 1000 0 1 1000 0 1 1000 0 1 uuuu uu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu note: u stands for unchanged x stands for unknown stands for unimplemented ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 53 february 17, 2011 ht68f04 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 0 0 0 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu tbhp xxx uuu uuu uuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 00 00 00 uu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0 00 0 00 0 00 0 00 0 00 0 00 u uu u uu intc2 0 0 0 0 0 0 u u mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi2 00 00 00 00 00 00 uu uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu prm 0101 0000 0101 0000 0101 0000 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0.011 0111 0011 0111 uuuu uuuu eea xx xxxx xx xxxx xx xxxx uu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu cpc 1000 0 1 1000 0 1 1000 0 1 uuuu uu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu note: u stands for unchanged x stands for unknown stands for unimplemented ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 54 february 17, 2011 input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output opera - tion, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list register name bit 76543210 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external re - sistor. to eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using the register papu, and are implemented using weak pmos transistors. papu register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 pawu : port a bit 7 ~ bit 0 wake-up control 0: disable 1: enable ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 55 february 17, 2011 i/o port control register the i/o port has its own control register known as pac, to control the input/output configuration. with this control regis - ter, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o port is di - rectly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by in - structions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos out - put. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por11111111 bit 7~0 i/o port bit 7 ~ bit 0 input/output control 0: output 1: input pin-remapping functions the flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. the way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. additionally there is a prm register to establish certain pin functions. generally speaking, the analog function has higher priority than the digital function. however, if more than two analog functions are enabled and the analog signal input comes from the same external pin, the analog input will be internally connected to all of these active analog functional mod- ules. pin-remapping registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. pin-remapping register list register name bit 76543210 prm prml3 prml2 prml1 prml0 prms2 prms1 prms0 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 56 february 17, 2011 prm register ht66f03/ht68f03/ht68f04 bit76543210 name prml3 prml2 prml1 prml0 prms2 prms1 prms0 r/w r/w r/w r/w r/w r/w r/w r/w por0101 000 bit 7~4 prml3~prml0 : pin-remapping function lock bits (default: 0101) 1010: prm register write operation is enabled others: prm register write operation is disabled bit 3 unimplemented, read as 0 bit 2 prms2 : int/tck1 pin-remapping function selection bit 1: int on pa7, tck1 on pa7. 0: int on pa3, tck1 on pa3. bit 1~0 prms1~prms0 : pin-remapping function selection bits 0x: tp0 on pa3, tp1/tck0 on pa4. 10: tp0 on pa5, tp1/tck0 on pa6. 11: tp0 on pa2, tp1/tck0 on pa7. ht66f04 bit76543210 name prml3 prml2 prml1 prml0 prms2 prms1 prms0 r/w r/w r/w r/w r/w r/w r/w r/w por0101 000 bit 7~4 prml3~prml0 : pin-remapping function lock bits (default: 0101) 1010: prm register write operation is enabled others: prm register write operation is disabled bit 3 unimplemented, read as 0 bit 2 prms2 : int/tck1 pin-remapping function selection bit 1: int on pa7, tck1 on pa7. 0: int on pa3, tck1 on pa3. bit 1~0 prms1~prms0 : pin-remapping function selection bits 00: tp0/tck2 on pa3, tp1/tck0 on pa4, tp2b on pa5, tp2a on pa6 01: tp0/tck2 on pa3, tp1/tck0 on pa4, tp2b on pa0, tp2a on pa1 10: tp0/tck2 on pa5, tp1/tck0 on pa6, tp2b on pa2, tp2a on pa7 11: tp0/tck2 on pa2, tp1/tck0 on pa7, tp2b on pa5, tp2a on pa6 i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the first things to con - sider is port initialisation. after a reset, all of the i/o data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port con - trol register, pac, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register, pa, is first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port con - trol register or by programming individual bits in the port control register using the set [m].i and clr [m].i in - structions. note that when using these bit control in - structions, a read-modify-write operation takes place. the microcontroller must first read in the data on the en - tire port, modify it to the required new bit values and then rewrite this data back to the output ports. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 57 february 17, 2011 the power-on reset condition of the a/d converter con - trol registers ensures that any a/d input pins - which are always shared with other i/o functions - will be setup as analog inputs after a reset. although these pins will be configured as a/d inputs after a reset, the a/d converter will not be switched on. it is therefore important to note that if it is required to use these pins as i/o digital input pins or as other functions, the a/d converter control reg - isters must be correctly programmed to remove the a/d function. note also that as the a/d channel is enabled, any internal pull-high resistor connections will be re - moved. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. = 5 c : . ? ! : . ? # & g > g > 9 9 : & % # & : & 9 6 ( g g 4 $ ! : . 4 ? 4 ? / & % & generic input/output structure = 5 c # & 9 9 : & % # & : & 9 $ ( 6 4 $ < $ $ ( ) : . 4 ? $ & 6 g > g g > g 4 ? / & % & a/d input/output structure ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 58 february 17, 2011 timer modules tm one of the most fundamental functions in any microcontroller device is the ability to control and mea - sure time. to implement time related functions each de - vice includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse out - put as well as being the functional unit for the generation of pwm signals. each of the tms has either two or three individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and flexible range of features. the common features of the different tm types are de - scribed here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devices contain from three to four tms depending upon which device is selected with each tm having a reference name of tm0, tm1 and tm2. each individual tm can be categorised as a certain type, namely com - pact type tm, standard type tm or enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact, standard and enhanced tms will be described in this section, the detailed operation regard - ing each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompa - nying table. function ctm stm etm timer/counter i/p capture compare match output pwm channels 1 1 2 single pulse output 12 pwm alignment edge edge edge & centre pwm adjustment period & duty duty or period duty or period duty or period tm function summary each device in the series contains a specific number of either compact type, standard type and enhanced type tm units which are shown in the table together with their individual reference name, tm0~tm2. device tm0 tm1 tm2 ht66f03/ht68f03/ht68f04 10-bit ctm 10-bit stm ht66f04 10-bit ctm 10-bit stm 10-bit etm tm name/type reference ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 59 february 17, 2011 tm operation the three different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm oper - ates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in effect dis - connecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two in- ternal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm out - put pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is es - sentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this ex - ternal tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have one or more output pins with the la - bel tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. the tpn pin acts as an input when the tm is setup to op - erate in the capture input mode. as the tpn pins are pin-shared with other functions, the tpn pin function is enabled or disabled according to the internal tm on/off control, operation mode and output control settings. when the corresponding tm configuration selects the tpn pin to be used as an output pin, the associated pin will be setup as an external tm output pin. if the tm con - figuration selects the tpn pin to be setup as an input pin, the input signal supplied on the associated pin can be derived from an external signal and other pin-shared output function. if the tm configuration determines that the tpn pin function is not used, the associated pin will be controlled by the other pin-shared functions. the number of tpn pins for each tm type and device is dif- ferent, for which details are provided in the accompany- ing table. device ctm stm etm ht66f03/ht68f03/ht68f04 tp0 tp1 ht66f04 tp0 tp1 tp2a, tp2b tm output pins ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 60 february 17, 2011 programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, being either 10-bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the mov instruction to access the ccra and ccrb low byte registers, named tmxal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. the following steps show the read and write procedures: writing data to ccrb or ccra step 1. write data to low byte tmxal or tmxbl - note that here data is only written to the 8-bit buffer. step 2. write data to high byte tmxah or tmxbh - here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. reading data from the counter registers and ccrb or ccra step 1. read data from the high byte tmxdh, tmxah or tmxbh - here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. step 2. read data from the low byte tmxdl, tmxal or tmxbl - this step reads data from the 8-bit buffer. data bus 8-bit buffer tmxdh tmxdl tmxbh tmxbl tmxah tmxal tm counter register (read only) tm ccra register (read/write) tm ccrb register (read/write) ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 61 february 17, 2011 compact type tm ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or two external output pin. these two external output pins can be the same sig - nal or the inverse signal. ctm name tm no. tm input pin tm output pin all devices 10-bit ctm 0 tck0 tp0 compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by chang - ing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected us - ing relevant internal registers. ! " # " ! ! ! " $ % " ! $ % " ! & % & % # ' # ! ! # ( ) * ) + , ( ) * ) ( - + . ( - + . , ( / " 0 " 1 " 2 compact type tm block diagram ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 62 february 17, 2011 compact type tm register description overall operation of the compact tm is controlled using six registers. a read only register pair exists to store the inter - nal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm0c0 t0pau t0ck2 t0ck1 t0ck0 t0on t0rp2 t0rp1 t0rp0 tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr tm0dl d7 d6 d5 d4 d3 d2 d1 d0 tm0dh d9 d8 tm0al d7 d6 d5 d4 d3 d2 d1 d0 tm0ah d9 d8 compact tm register list tm0dl register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr por00000000 bit 7~0 tm0dl : tm0 counter low byte register bit 7 ~ bit 0 tm0 10-bit counter bit 7 ~ bit 0 tm0dh register bit76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm0dh : tm0 counter high byte register bit 1 ~ bit 0 tm0 10-bit counter bit 9 ~ bit 8 tm0al register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm0al : tm0 ccra low byte register bit 7 ~ bit 0 tm0 10-bit ccra bit 7 ~ bit 0 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 63 february 17, 2011 tm0ah register bit76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm0ah : tm0 ccra high byte register bit 1 ~ bit 0 tm0 10-bit ccra bit 9 ~ bit 8 tm0c0 register bit76543210 name t0pau t0ck2 t0ck1 t0ck0 t0on t0rp2 t0rp1 t0rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t0pau : tm0 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t0ck2~t0ck0 : select tm0 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t0on : tm0 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the t0oc bit, when the t0on bit changes from low to high. bit 2~0 t0rp2~t0rp0 : tm0 ccrp 3-bit register, compared with the tm0 counter bit 9~bit 7 comparator p match period 000: 1024 tm0 clocks 001: 128 tm0 clocks 010: 256 tm0 clocks 011: 384 tm0 clocks 100: 512 tm0 clocks 101: 640 tm0 clocks 110: 768 tm0 clocks 111: 896 tm0 clocks ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 64 february 17, 2011 these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the t0cclr bit is set to zero. setting the t0cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm0c1 register bit76543210 name t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 t0m1~t0m0 : select tm0 operating mode 00: compare match output mode 01: undefined 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t0m1 and t0m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t0io1~t0io0 : select tp0 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefined timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t0oc bit in the tm0c1 register. note that the output level requested by the t0io1 and t0io0 bits must be different from the initial value setup using the t0oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t0on bit from low to high. in the pwm mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t0io1 and t0io0 bits only after the tmn has been switched off. unpredictable pwm outputs will occur if the t0io1 and t0io0 bits are changed when the tm is running bit 3 t0oc : tp0 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 65 february 17, 2011 this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t0pol : tp0 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp0 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t0dpx : tm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr : select tm0 counter clear condition 0: tm0 comparatror p match 1: tm0 comparatror a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t0cclr bit is not used in the pwm mode. compact type tm operating modes the compact type tm can operate in one of three oper- ating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overflow, a com - pare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both tnaf and tnpf interrupt request flags for the comparator a and comparator p re - spectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf inter - rupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt re - quest flag will be generated. if the ccra bits are all zero, the counter will overflow when its reaches its maxi - mum 10-bit, 3ff hex, value, however here the tnaf in - terrupt request flag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is generated after a com- pare match occurs from comparator a. the tnpf inter- rupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same in - terrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the com - pare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 66 february 17, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 67 february 17, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf flag is not generated when tncclr=1 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 68 february 17, 2011 pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm func - tion within the tm is useful for applications which require functions such as motor control, heating control, illumi - nation control etc. by providing a signal of fixed fre - quency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with vary - ing equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polar - ity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tnm [1:0] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) pwm mode -- tndpx = 0 note: 1. here tndpx=0 -- counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 69 february 17, 2011 counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tnm [1:0] = 10 pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) pwm mode -- tndpx = 1 note: 1. here tndp x=1-- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation ctm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the ctm pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defined by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cy - cle is defined by the ccrp register value. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 70 february 17, 2011 standard type tm - stm the standard type tm contains five operating modes, which are compare match output, timer/event counter, cap - ture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external in - put pin and can drive one or two external output pin. ctm name tm no. tm input pin tm output pin all devices 10-bit stm 1 tck1 tp1 ! " # " ! ! ! " $ % " ! $ % " ! 3 2 4 " 5 " " % & % & % & % # ' # ! ! # ( ) * ) + , ( ) * ) ( - + . ( - + . , ( / " 0 " 1 " 2 standard type tm block diagram standard tm operation at the core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 3-bit wide whose value is compared the with highest 3 bits in the counter while the ccra is the ten bits and therefore compares all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 71 february 17, 2011 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 tm1c1 t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr tm1dl d7 d6 d5 d4 d3 d2 d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d3 d2 d1 d0 tm1ah d9 d8 standard tm register list tm1c0 register bit76543210 name t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t1on : tm1 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the t1oc bit, when the t1on bit changes from low to high. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 72 february 17, 2011 bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm1c1 register bit76543210 name t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 t1m1~t1m0 : select tm1 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1m1 and t1m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0 : select tp1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1 01: input capture at falling edge of tp1 10: input capture at falling/rising edge of tp1 11: input capture disabled ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 73 february 17, 2011 timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1oc bit in the tm1c1 register. note that the output level requested by the t1io1 and t1io0 bits must be different from the initial value setup using the t1oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t1io1 and t1io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1io1 and t1io0 bits are changed when the tm is running bit 3 t1oc : tp1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1pol : tp1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1dpx : tm1 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparatror p match 1: tm1 comparatror a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 74 february 17, 2011 tm1dl register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr por00000000 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register bit76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm1al : tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 tm1ah register bit76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1ah : tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 75 february 17, 2011 standard type tm operating modes the standard type tm can operate in one of five oper - ating modes, compare match output mode, pwm out - put mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter over - flow, a compare match from comparator a and a com - pare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from compara - tor p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both tnaf and tnpf interrupt request flags for comparator a and com - parator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf inter - rupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt re - quest flag will be generated. in the compare match out - put mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is generated after a com - pare match occurs from comparator a. the tnpf inter - rupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 76 february 17, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf flag is not generated when tncclr=1 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 77 february 17, 2011 timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same in - terrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the com - pare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applica - tions which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be gen - erated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm wave - form, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 regis - ter. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polar - ity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tnm [1:0] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) pwm mode -- tndpx = 0 note: 1. here tndpx=0 -- counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 78 february 17, 2011 stm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the stm pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125khz, duty = 128/512 = 25%. if the duty value defined by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit stm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cy - cle is defined by the ccrp register value. counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tnm [1:0] = 10 pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) pwm mode -- tndpx = 1 note: 1. here tndpx=1 -- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 79 february 17, 2011 single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be imple - mented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse out - put. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trail - ing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from com - parator a. " 2 4 3 2 4 " ) + 6 2 ) 3 7 7 0 ) + 6 2 7 7 " ! # 0 " 6 2 8 9 # ! " # 4 3 2 4 " ! ! single pulse generation counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high tnm [1:0] = 10 ; tnio [1:0] = 11 pulse width set by ccra output inverts when tnpol = 1 no ccrp interrupts generated tm o/p pin (tnoc=0) tckn pin software trigger cleared by ccra match tckn pin trigger auto. set by tckn pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 80 february 17, 2011 however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm inter - rupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode. capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively. this mode en - ables the external signal to capture and store the pres - ent value of the internal counter and can therefore be used for applications such as pulse width measure - ments. the external signal is supplied on the tp1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp1 pin, the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irre - spective of what events occur on the tp1 pin the coun - ter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from com - parator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tp1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tp1 pin, how - ever it must be noted that the counter will continue to run. as the tp1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture oper - ation to be executed. the tncclr and tndpx bits are not used in this mode. counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counter cleared by ccrp pause resume counter reset tnm [1:0] = 01 tm capture pin tpn_x xx counter stop tnio [1:0] value xx yy xx yy active edge active edge active edge 00 rising edge 01 fallin g edge 10 both edges 11 disable capture capture input mode note: 1. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the tncclr bit is not used 4. no output function -- tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 81 february 17, 2011 enhanced type tm etm the enhanced type tm contains five operating modes, which are compare match output, timer/event counter, cap - ture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external in - put pin and can drive three or two external output pins. ctm name tm no. tm input pin tm output pin ht66f03/ht68f03/ht68f04 ht66f04 10-bit etm 2 tck2 tp2a, tp2b ! " # " $ % & ! " ' ( " ! ' ( " ! ) * + " % " " ( , ( , ( , ( # - # ! ! # . / 0 / $ 1 . / 0 / . 2 $ 3 . 2 $ 3 1 . 4 " 5 " 6 " * 4 ' ( " ! 4 , 4 4 ( , 4 ( 4 4 # - # ! ! # 4 4 4 ) * + " % " " ( , ( 4 enhanced type tm block diagram enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and com - parator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore com - pared with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 82 february 17, 2011 enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm2c0 t2pau t2ck2 t2ck1 t2ck0 t2on t2rp2 t2rp1 t2rp0 tm2c1 t2am1 t2am0 t2aio1 t2aio0 t2aoc t2apol t2cdn t2cclr tm2c2 t2bm1 t2bm0 t2bio1 t2bio0 t2boc t2bpol t2pwm1 t2pwm0 tm2dl d7 d6 d5 d4 d3 d2 d1 d0 tm2dh d9 d8 tm2al d7 d6 d5 d4 d3 d2 d1 d0 tm2ah d9 d8 tm2bl d7 d6 d5 d4 d3 d2 d1 d0 tm2bh d9 d8 10-bit enhanced tm register list 10-bit enhanced tm register list - ht66f04 tm2c0 register bit76543210 name t2pau t2ck2 t2ck1 t2ck0 t2on t2rp2 t2rp1 t2rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t2pau : tm2 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2~t2ck0 : select tm2 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t2on : tm2 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 83 february 17, 2011 if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the t2aoc or t2boc bit, when the t2on bit changes from low to high. bit 2~0 t2rp2~t2rp0 : tm2 ccrp 3-bit register, compared with the tm2 counter bit 9~bit 7 comparator p match period 000: 1024 tm2 clocks 001: 128 tm2 clocks 010: 256 tm2 clocks 011: 384 tm2 clocks 100: 512 tm2 clocks 101: 640 tm2 clocks 110: 768 tm2 clocks 111: 896 tm2 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the t2cclr bit is set to zero. setting the t2cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm2c1 register bit76543210 name t2am1 t2am0 t2aio1 t2aio0 t2aoc t2apol t2cdn t2cclr r/w r/w r/w r/w r/w r/w r/w r r/w por00000000 bit 7~6 t2am1~t2am0 : select tm2 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t2am1 and t2am0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t2aio1~t2aio0 : select tp2a output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2a 01: input capture at falling edge of tp2a 10: input capture at falling/rising edge of tp2a 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 84 february 17, 2011 in the compare match output mode, the t2aio1 and t2aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2aoc bit in the tm2c1 register. note that the output level requested by the t2aio1 and t2aio0 bits must be different from the initial value setup using the t2aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2aio1 and t2aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t2aio1 and t2aio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t2aio1 and t2aio0 bits are changed when the tm is running. bit 3 t2aoc : tp2a output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2apol : tp2a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t2cdn : tm2 counter count up or down flag 0: count up 1: count down bit 0 t2cclr : select tm2 counter clear condition 0: tm2 comparator p match 1: tm2 comparator a match this bit is used to select the method which clears the counter. remember that the enhanced tm contains three comparators, comparator a, comparator b and comparator p, but only comparator a or comparator p can be selected to clear the internal counter. with the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t2cclr bit is not used in the pwm, single pulse or input capture mode. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 85 february 17, 2011 tm2c2 register bit76543210 name t2bm1 t2bm0 t2bio1 t2bio0 t2boc t2bpol t2pwm1 t2pwm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 t2bm1~t2bm0 : select tm2 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t2bm1 and t2bm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t2bio1~t2bio0 : select tp2b output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2b 01: input capture at falling edge of tp2b 10: input capture at falling/rising edge of tp2b 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t2bio1 and t2bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2boc bit in the tm2c2 register. note that the output level requested by the t2bio1 and t2bio0 bits must be different from the initial value setup using the t2boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2bio1 and t2bio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t2bio1 and t2bio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t2bio1 and t2bio0 bits are changed when the tm is running. bit 3 t2boc : tp2b output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 86 february 17, 2011 this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2bpol : tp2b output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2b output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1~0 t2pwm1~t2pwm0 : select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm2dl register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr por00000000 bit 7~0 tm2dl : tm2 counter low byte register bit 7~bit 0 tm2 10-bit counter bit 7~bit 0 tm2dh register bit76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm2dh : tm2 counter high byte register bit 1~bit 0 tm2 10-bit counter bit 9~bit 8 tm2al register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm2al : tm2 ccra low byte register bit 7~bit 0 tm2 10-bit ccra bit 7~bit 0 tm2ah register bit76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm2ah : tm2 ccra high byte register bit 1~bit 0 tm210-bit ccra bit 9~bit 8 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 87 february 17, 2011 tm2bl register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit7~0 tm2bl : tm2 ccrb low byte register bit 7~bit 0 tm2 10-bit ccrb bit 7~bit 0 tm2bh register bit76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm2bh : tm2 ccrb high byte register bit 1~bit 0 tm2 10-bit ccrb bit 9 ~ bit 8 enhanced type tm operating modes the enhanced type tm can operate in one of five operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operating mode ccra compare match output mode ccra timer/counter mode ccra pwm output mode ccra single pulse output mode ccra input capture mode ccrb compare match output mode ccrb timer/counter mode ccrb pwm output mode ccrb single pulse output mode ccrb input capture mode : permitted : not permitted compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all cleared to zero. in this mode once the counter is en - abled and running it can be cleared by three methods. these are a counter overflow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a com - pare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both the tnaf and tnpf interrupt re - quest flags for comparator a and comparator p respec - tively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf inter - rupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt re - quest flag will be generated. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 88 february 17, 2011 as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf or tnbf interrupt request flag is generated af - ter a compare match occurs from comparator a or com - parator b. the tnpf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tpnb pins) to go high, to go low or to toggle from its present condi - tion when a compare match occurs from comparator a or a compare match occurs from comparator b. the ini - tial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna or tpnb output pin. note that if the tnaio1,tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place. counter value 0x3ff ccrp ccra tnon tnpau tnapol ccrp int. flag tnpf ccra int. flag tnaf tpna o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnam [1:0] = 00 output pin set to initial level low if tnaoc=0 output toggle with tnaf flag note tnaio [1:0] = 10 active high output select here tnaio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high etm ccra compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 89 february 17, 2011 counter value 0x3ff ccrp ccrb tnon tnpau tnbpol ccrp int. flag tnpf ccrb int. flag tnbf tpnb o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnbm [1:0] = 00 output pin set to initial level low if tnboc=0 output toggle with tnbf flag note tnbio [1:0] = 10 active high output select here tnbio [1:0] = 11 toggle output select output not affected by tnbf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high etm ccrb compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf flag 3. the output pin is reset to its initial state by a tnon bit rising edge ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 90 february 17, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnapol ccrp int. flag tnpf ccra int. flag tnaf tpna o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnam [1:0] = 00 output pin set to initial level low if tnaoc=0 output toggle with tnaf flag note tnaio [1:0] = 10 active high output select here tnaio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change etm ccra compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf flag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf flag is not generated when tncclr=1 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 91 february 17, 2011 counter value 0x3ff ccrb ccra tnon tnpau tnbpol ccrb int. flag tnbf ccra int. flag tnaf tpnb o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnbm [1:0] = 00 output pin set to initial level low if tnboc=0 output toggle with tnbf flag note tnbio [1:0] = 10 active high output select here tnbio [1:0] = 11 toggle output select output not affected by tnbf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high no tnaf flag generated on ccra overflow etm ccrb compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf flag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf flag is not generated when tncclr=1 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 92 february 17, 2011 timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 register should all be set high. the timer/counter mode operates in an identi - cal way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to un - derstand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respec - tively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which re - quire functions such as motor control, heating control, il - lumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is con- trolled. with the tncclr bit set high, the pwm period can be finely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty value (for tpnb output pin). the ccrp bits are not used and tpna output pin is not used. the pwm output can only be generated on the tpnb output pin. with the tncclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multi - ples of 128. now both ccra and ccrb registers can be used to setup different duty cycle values to provide dual pwm outputs on their relative tpna and tpnb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is re - set to zero. with all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially, thus reduc - ing the level of simultaneous power switching currents. interrupt flags, one for each of the ccra, ccrb and ccrp, will be generated when a compare match occurs from either the comparator a, comparator b or com - parator p. the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform. etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 a duty ccra b duty ccrb if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b, ccra = 128 and ccrb = 256, the tp1a pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125khz, duty = 128/512 = 25%. the tp1b_n pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125khz, duty = 256/512 = 50%. if the duty value defined by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 1 2 3 511 512 1021 1022 1023 b duty ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 256 512 768 1024 1280 1536 1792 2046 a duty (ccra2) 1 b duty (ccrb2) 1 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 93 february 17, 2011 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 2 4 6 1022 1024 2042 2044 2046 b duty (ccrb2) 1 counter value ccrp ccra tnon tnpau tnapol ccra int. flag tnaf ccrb int. flag tnbf tpna pin (tnaoc=1) time counter cleared by ccrp pause resume stop counter restart tncclr = 0; tnam [1:0] = 10, tnbm [1:0] = 10; tnpwm [1:0] = 00 output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp duty cycle set by ccra duty cycle set by ccra etm pwm mode -- edge aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 94 february 17, 2011 counter value ccra tnon tnpau tnbpol ccrb int. flag tnbf time counter cleared by ccra pause resume stop counter restart tncclr = 1; tnbm [1:0] = 10; tnpwm [1:0] = 00 output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccrb pwm period set by ccra etm pwm mode -- edge aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 3. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 95 february 17, 2011 counter value ccrp ccra tnon tnpau tnapol ccra int. flag tnaf ccrb int. flag tnbf tpna pin (tnaoc=1) time pause resume stop counter restart tncclr = 0; tnam [1:0] = 10, tnbm [1:0] = 10; tnpwm [1:0] = 11 output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp etm pwm mode -- centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 96 february 17, 2011 counter value ccra tnon tnpau tnbpol ccra int. flag tnaf ccrb int. flag tnbf time pause resume stop counter restart tncclr = 1; tnbm [1:0] = 10; tnpwm [1:0] = 11 output pin reset to initial value output controlled by other pin-shared function ccrb tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccrb pwm period set by ccra output inverts when tnbpol is high ccrp int. flag tnpf etm pwm mode -- centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 97 february 17, 2011 single pulse output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respec - tively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be im - plemented using the application program. the trigger for the pulse tpnb output leading edge is a compare match from comparator b, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automat - ically change from low to high using the external tckn pin, which will in turn initiate the single pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb will be generated when the tnon bit is cleared to zero, which can be im - plemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb. in this way the ccra value can be used to control the pulse width of tpna. the ccra-ccrb value can be used to control the pulse width of tpnb. a compare match from comparator a and comparator b will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. single pulse generation ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 98 february 17, 2011 counter value ccrb ccra tnon tnpau tnapol ccrb int. flag tnbf ccra int. flag tnaf tpna pin (tnaoc=1) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high tnam [1:0] = 10, tnbm [1:0] = 10; tnaio [1:0] = 11, tnbio [1:0] = 11 pulse width set by (ccra-ccrb) output inverts when tnbpol=1 tckn pin software trigger cleared by ccra match tckn pin trigger auto. set by tckn pin software trigger software clear software trigger software trigger tnbpol tpna pin (tnaoc=0) tpnb pin (tnboc=1) tpnb pin (tnboc=0) pulse width set by ccra output inverts when tnapol=1 etm -- single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 11 and can not be changed. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 99 february 17, 2011 capture input mode to select this mode bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively. this mode enables external sig - nals to capture and store the present value of the inter - nal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpna and tpnb pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna and tpnb pins the present value in the counter will be latched into the ccra and ccrb registers and a tm in - terrupt generated. irrespective of what events occur on the tpna and tpnb pins the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm inter - rupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a use - ful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can select the active trigger edge on the tpna and tpnb pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpna and tpnb pins, however it must be noted that the counter will continue to run. as the tpna and tpnb pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an out - put, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are not used in this mode. counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counter cleared by ccrp pause resume counter reset tnam [1:0] = 01 tm capture pin tpna xx counter stop tnaio [1:0] value xx yy xx yy active edge active edge active edge 00 rising edge 01 fallin g edge 10 both edges 11 disable capture etm ccra capture input mode note: 1. tnam [1:0] = 01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccra 3. the tncclr bit is not used 4. no output function -- tnaoc and tnapol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 100 february 17, 2011 counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccrb int. flag tnbf ccrb value time counter cleared by ccrp pause resume counter reset tnbm [1:0] = 01 tm capture pin tpnb_x xx counter stop tnbio [1:0] value xx yy xx yy active edge active edge active edge 00 rising edge 01 fallin g edge 10 both edges 11 disable capture etm ccrb capture input mode note: 1. tnbm [1:0] = 01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. the tncclr bit is not used 4. no output function -- tnboc and tnbpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 101 february 17, 2011 analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d con - version electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. a/d overview the devices contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control sig - nals and convert these signals directly into either a 12-bit digital value. part no. input channels a/d channel select bits input pins ht66f03 ht66f04 4 acs4, acs1~acs0 an0~an3 the accompanying block diagram shows the overall in - ternal structure of the a/d converter, together with its as - sociated registers. a/d converter register description overall operation of the a/d converter is controlled us - ing five registers. a read only register pair exists to store the adc data 12-bit value. the remaining three regis - ters are control registers which setup the operating and control function of the a/d converter. register name bit 76543210 adrl(adrfs=0) d3 d2 d1 d0 adrl(adrfs=1) d7 d6 d5 d4 d3 d2 d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs1 acs0 adcr1 acs4 v125en vrefs adck2 adck1 adck0 acerl ace3 ace2 ace1 ace0 ht66f03/ht66f04 a/d converter register list a/d converter data registers adrl, adrh as the devices contain an internal 12-bit a/d converter, they require two data registers to store the converted value. these are a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7654321076543210 0 d11d10d9d8d7d6d5d4d3d2d1d00000 1 0000d11d10d9d8d7d6d5d4d3d2d1d0 a/d data registers ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 102 february 17, 2011 ! ! " # " $ $ $ % & % ' & ( ) & * + " $ $ # $ # $ , - . & / 0 a/d converter structure a/d converter control registers adcr0, adcr1, acerl to control the function and operation of the a/d con - verter, three control registers known as adcr0, adcr1 and acerl are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs1~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register de - fine the adc input channel number. as the device con - tains only one actual analog to digital converter hardware circuit, each of the individual 4 analog inputs must be routed to the converter. it is the function of the acs4, acs1 and acs0 bits to determine which analog channel input pins or internal 1.25v is actually con - nected to the internal a/d converter. the acerl control register contains the acer3~ acer0 bits which determine which pins on port a are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d in - put function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is se - lected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is se - lected to be an a/d input. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 103 february 17, 2011 adcr0 register ht66f03/ht66f04 bit76543210 name start eocb adoff adrfs acs1 acs0 r/w r/w r r/w r/w r/w r/w por0110 00 bit 7 start : start the a/d conversion 01 0 : start 0 1 : reset the a/d converter and set eocb to 1 this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion flag 0: a/d conversion ended 1: a/d conversion in progress this read only flag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~2 unimplemented, read as 0 bit 1~0 acs1, acs0 : select a/d channel (when acs4 is 0) 00: an0 01: an1 10: an2 11: an3 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the four a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high, then the internal 1.25v reference voltage source will be routed to the a/d converter. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 104 february 17, 2011 adcr1 register ht66f03/ht66f04 bit76543210 name acs4 v125en vrefs adck2 adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 000 bit 7 acs4 : selecte internal 1.25v as adc input control 0: disable 1: enable this bit enables 1.25v to be connected to the a/d converter. the v125en bit must first have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v125en : internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the bandgap voltage 1.25v can be used by the a/d converter. if 1.25v is not used by the a/d converter and the lvr/lvd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as 0 bit 4 vrefs : selecte adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter. if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. when the a/d converter reference voltage is supplied on the external vref pin which is pin-shared with other functions, all of the pin-shared functions except vref on this pin are disabled. bit 3 unimplemented, read as 0 bit 2~0 adck2, adck1, adck0 : select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefined these three bits are used to select the clock source for the a/d converter. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 105 february 17, 2011 acerl register ht66f03/ht66f04 bit76543210 name ace3 ace2 ace1 ace0 r/w r/w r/w r/w r/w por 1111 bit 7~4 unimplemented, read as 0 bit 3 ace3 : define pa3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : define pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : define pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : define pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the start bit in the adcr0 register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an ana- log to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall start opera - tion of the internal analog to digital converter. the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is com - plete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the inter - rupts are enabled, an appropriate internal interrupt sig - nal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d inter - nal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/d clock source is determined by the sys- tem clock f sys , and by bits adck2~adck0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of per - missible a/d clock period, t adck , is from 0.5 sto10 s, care must be taken for selected system clock frequen - cies. for example, if the system clock operates at a fre - quency of 4mhz, the adck2~adck0 bits should not be set to 000b or 110b . doing so will give a/d clock peri - ods that are less than the minimum a/d clock period or greater than the maximum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum a/d clock period. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 106 february 17, 2011 f sys a/d clock period (t adck ) adck2, adck1, adck0 = 000 (f sys ) adck2, adck1, adck0 = 001 (f sys /2) adck2, adck1, adck0 = 010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 = 100 (f sys /16) adck2, adck1, adck0 = 101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 = 111 1mhz 1s2 s4 s8 s16 s* 32 s* 64s* undefined 2mhz 500ns 1s2 s4 s8 s16 s* 32s* undefined 4mhz 250ns* 500ns 1s2 s4 s8 s16 s* undefined 8mhz 125ns* 250ns* 500ns 1s2 s4 s8 s undefined 12mhz 83ns* 167ns* 333ns* 667ns 1.33 s 2.67 s 5.33s undefined a/d clock period examples controlling the power on/off function of the a/d con - verter circuitry is implemented using the adoff bit in the adcr0 register. this bit must be zero to power on the a/d converter. when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace3~ace0 bits in the acerl registers, if the adoff bit is zero then some power will still be con - sumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref. the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a as well as other functions. the ace3~ ace0 bits in the acerl register, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace3~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to first setup the a/d pin as an input in the pac port control register to enable the a/d input as when the ace3~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be sup - plied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the ana - log input values must not be allowed to exceed the value of vref. summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d con - version process. step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 reg - ister. step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4, acs1 and acs0 bits which are also contained in the adcr1 and adcr0 register. step 4 select which pins are to be used as a/d inputs and configure them by correctly programming the ace3~ace0 bits in the acerl register. * # 1 $ $ $ 2 , # 3 4 5 4 1 ( ) & a/d input structure ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 107 february 17, 2011 step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter inter - rupt bit, eadi, must both be set high to do this. step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr regis - ter from low to high and then low again. note that this bit should have been originally cleared to zero. step 7 to check when the analog to digital conversion pro - cess is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method, if the in - terrupts are enabled and the stack is not full, the pro - gram can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the vari - ous stages involved in an analog to digital conversion process and its associated timing. after an a/d conver - sion process has been initiated by the application pro- gram, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t adck where t adck is equal to the a/d clock period. programming considerations during microcontroller operations where the a/d con - verter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. the power-on reset condition of the a/d converter con - trol registers will ensure that the shared function pins are setup as a/d converter inputs. if any of the a/d con - verter input pins are to be used for functions, then the a/d converter control register bits must be properly setup to disable the a/d input configuration. a/d transfer function as the devices contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (v dd or v ref ) 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the off - set, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level. a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the first example, the method of polling the eocb bit in the adcr0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 108 february 17, 2011 $ $ - 0 1 $ $ $ $ $ * # ( 6 ( 6 ( ( 6 ( 6 / 5 4 1 * # $ ( 6 / ideal a/d transfer function 7 # # ! ! " # ( ) ) 8 2 3 9 4 1 9 : 7 4 7 # # 3 7 4 7 " ! 7 " $ $ ; 3 1 " a/d conversion timing ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 109 february 17, 2011 example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acerl to configure pins an0~an3 mov acerl,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : jmp start_conversion ; start next a/d conversion example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acerl to configure pins an0~an3 mov acerl,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defined memory mov a,status mov status_stack,a ; save status to user defined memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory reti ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 110 february 17, 2011 comparators an analog comparator is contained within these de - vices. these functions offer flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. comparator operation the device contains a comparator function which is used to compare two analog voltages and provide an output based on their difference. full control over the in - ternal comparators is provided via the control register cpc assigned to the comparator. the comparator out - put is recorded via a bit in the control register, but can also be transferred out onto a shared i/o pin. additional comparator functions include, output polarity, hysteresis functions and power down control. any pull-high resistors connected to the shared com- parator input pins will be automatically disconnected when the comparator is enabled. as the comparator in- puts approach their switching level, some spurious out- put signals may be generated on the comparator output due to the slow rising or falling nature of the input sig- nals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the positive and negative inputs sig - nals are at the same voltage level, however, unavoid - able input offsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator interrupt the comparator possesses its own interrupt function. when the comparator output changes state, its relevant interrupt flag will be set, and if the corresponding inter - rupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the cout bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt flag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port con- trol register is 1 ) or read as port data register value (port control register is 0 ) if the comparator function is enabled. < 2 " " = ! > comparator ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 111 february 17, 2011 cpc register bit76543210 name csel cen cpol cout cos chyen r/w r/w r/w r/w r r/w r/w por10000 1 bit 7 csel : select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. bit 6 cen : comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 cpol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the cout bit will reflect the non-inverted output condition of the comparator. if the bit is high the comparator cout bit will be inverted. bit 4 cout : comparator output bit cpol=0 0: c+ < c- 1: c+ > c- cpol=1 0: c+ > c- 1: c+ < c- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the cpol bit. bit 3 cs : output path select 0: cx pin 1: internal use this is the comparator output path select control bit. if the bit is set to 0 and the csel bit is 1 the comparator output is connected to an external cx pin. if the bit is set to 1 or the csel bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as 0 bit 0 chyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 112 february 17, 2011 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main pro - gram allowing the microcontroller to direct attention to their respective needs. the device contains several ex - ternal interrupt and internal interrupts functions. the ex - ternal interrupt is generated by the action of the external int pin, while the internal interrupts are generated by various internal functions such as the tms, comparator, time base, lvd, eeprom, sim and the a/d converter. interrupt registers overall interrupt control, which basically means the set - ting of request flags when certain microcontroller condi - tions occur and the setting of interrupt enable bits by the application program, is controlled by a series of regis - ters, located in the special purpose data memory, as shown in the accompanying table. the number of regis - ters depends upon the device chosen but fall into three categories. the first is the intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi2 registers which setup the multi-function in - terrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual interrupts as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specific pattern. first is listed an abbreviated interrupt type, then the (op - tional) number of that interrupt followed by either an e for enable/disable bit or f for request flag. function enable bit request flag notes global emi int pin inte intf comparator cpe cpf a/d converter ade adf multi-function mfne mfnf n=0~2 time base tbne tbnf n=0~1 lvd lve lvf eeprom dee def tm tnpe tnpf n=0~2 tnae tnaf tnbe tnbf n=2 interrupt register bit naming conventions interrupt register contents ht66f03 name bit 76543210 integ ints1 ints0 intc0 mf0f cpf intf mf0e cpe inte emi intc1 tb0f adf mf2f tb0e ade mf2e intc2 tb1f tb1e mfi0 t1af t1pf t0af t0pf t1ae t1pe t0ae t0pe mfi1* reserved mfi2 def lvf dee lve * mfi1 register is reserved for advanced expansion. it is recommended that do not access the mfi1 register and keep its initial setting to avoid malfunction. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 113 february 17, 2011 ht66f04 name bit 76543210 integ ints1 ints0 intc0 mf0f cpf intf mf0e cpe inte emi intc1 tb0f adf mf2f mf1f tb0e ade mf2e mf1e intc2 tb1f tb1e mfi0 t1af t1pf t0af t0pf t1ae t1pe t0ae t0pe mfi1 t2bf t2af t2pf t2be t2ae t2pe mfi2 def lvf dee lve ht68f03/ht68f04 name bit 76543210 integ ints1 ints0 intc0 mf0f cpf intf mf0e cpe inte emi intc1 tb0f mf2f tb0e mf2e intc2 tb1f tb1e mfi0 t1af t1pf t0af t0pf t1ae t1pe t0ae t0pe mfi1* reserved mfi2 def lvf dee lve * mfi1 register is reserved for advanced expansion. it is recommended that do not access the mfi1 register and keep its initial setting to avoid malfunction. integ register bit76543210 name ints1 ints0 r/w r/w r/w por 11 bit 7~2 unimplemented, read as 0 bit 1~0 ints1, ints0 : interrupt edge control for int pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 114 february 17, 2011 intc0 register bit76543210 name mf0f cpf intf mf0e cpe inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 5 cpf : comparator interrupt request flag 0: no request 1: interrupt request bit 4 intf : int pin interrupt request flag 0: no request 1: interrupt request bit 3 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 2 cpe : comparator interrupt control 0: disable 1: enable bit 1 inte : int interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable intc1 register ht66f03 bit76543210 name tb0f adf mf2f tb0e ade mf2e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 000 bit 7 tb0f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 reserved and can not be used, read as 0 bit 3 tb0e : time base 0 interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 0 reserved and can not be used, read as 0 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 115 february 17, 2011 ht66f04 bit76543210 name tb0f adf mf2f mf1f tb0e ade mf2e mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 tb0f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 3 tb0e : time base 0 interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 0 mf1e : multi-function interrupt control 0: disable 1: enable ht68f03/ht68f04 bit76543210 name tb0f mf2f tb0e mf2e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb0f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 6 unimplemented, read as 0 bit 5 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 reserved and can not be used, read as 0 bit 3 tb0e : time base 0 interrupt control 0: disable 1: enable bit 2 unimplemented, read as 0 bit 1 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 0 reserved and can not be used, read as 0 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 116 february 17, 2011 intc2 register bit76543210 name tb1f tb1e r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as 0 bit 4 tb1f : time base 1 interrupt request flag 0: no request 1: interrupt request bit 3~1 unimplemented, read as 0 bit 0 tb1e : time base 1 interrupt control 0: disable 1: enable mfi0 register bit76543210 name t1af t1pf t0af t0pf t1ae t1pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t1af : tm1 comparator a match interrupt request flag 0: no request 1: interrupt request bit 6 t1pf : tm1 comparator p match interrupt request flag 0: no request 1: interrupt request bit 5 t0af : tm0 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 2 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 117 february 17, 2011 mfi1 register ht66f04 bit76543210 name t2bf t2af t2pf t2be t2ae t2pe r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 t2bf : tm2 comparator b match interrupt request flag 0: no request 1: interrupt request bit 5 t2af : tm2 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t2pf : tm2 comparator b match interrupt request flag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 t2be : tm2 comparator p match interrupt control 0: disable 1: enable bit 1 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable mfi2 register bit76543210 name def lvf dee lve r/w r/w r/w r/w r/w por 00 00 bit 7~6 unimplemented, read as 0 bit 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 118 february 17, 2011 interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p, comparator a or comparator b match or a/d conversion completion etc, the relevant in - terrupt request flag will be set. whether the request flag actually generates a program jump to the relevant inter - rupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be ex - ecuted, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another sec - tion of program which is known as the interrupt service routine. here is located the code to control the appropri - ate interrupt. the interrupt service routine must be ter - minated with a reti , which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any fur - ther interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the re - quest flag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to al - low interrupt nesting. if the stack is full, the interrupt re - quest will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decre - mented. if immediate service is desired, the stack must be prevented from becoming full. in case of simulta - neous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request flags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occur - ring the corresponding flag should be set before the de - vice is in sleep or idle mode. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 119 february 17, 2011 04h 08h 0ch 14h 18h 1ch vector low priority high request flags enable bits master enable request flags enable bits emi auto disabled in isr in te rrup ts co ntain ed with in multi-function interrupts interrupt name interrupt name emi emi emi emi emi lvf lvd lve def eeprom dee t1af tm1 a t1ae t1pf tm1 p t1pe intf int pin inte cpf comparator cpe mf0f m. funct. 0 mf0e mf2f m. funct. 2 mf2e adf a/d ade emi tb0f time base 0 tb0e xxf legend request flag ? no auto reset in isr xxf request flag ? auto reset in isr xxe enable bit t0af tm0 a t0pf tm0 p t0ae t0pe 20h emi tb1f time base 1 tb1e interrupt structure ht66f03 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 120 february 17, 2011 04h 08h 0ch 14h 18h 1ch vector low priority high request flags enable bits master enable request flags enable bits emi auto disabled in isr in te rrupts co ntaine d with in mu lti-fu nctio n in terrup ts in te rrup t name in terrup t name emi emi emi emi emi lvf lvd lve def eeprom dee t1af tm1 a t1ae t1pf tm1 p t1pe intf int pin inte cpf comparator cpe mf0f m. funct. 0 mf0e mf2f m. funct. 2 mf2e adf a/d ade emi tb0f time base 0 tb0e xxf legend request flag ? no auto reset in isr xxf request flag ? auto reset in isr xxe enable bit t0af tm0 a t0pf tm0 p t0ae t0pe 20h emi tb1f time base 1 tb1e t2af tm2 a t2ae t2pf tm2 p t2pe t2bf tm2 b t2be 10h emi mf1f m. funct. 1 mf1e interrupt structure ht66f04 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 121 february 17, 2011 04h 08h 0ch 14h 1ch vector low priority high request flags enable bits master enable request flags enable bits emiautodisabledinisr in te rrup ts co ntain ed with in multi-function interrupts interrupt name interrupt name emi emi emi emi emi lvf lvd lve def eeprom dee t1af tm1 a t1ae t1pf tm1 p t1pe intf int pin inte cpf comparator cpe mf0f m. funct. 0 mf0e mf2f m. funct. 2 mf2e tb0f time base 0 tb0e xxf legend request flag ? no auto reset in isr xxf request flag ? auto reset in isr xxe enable bit t0af tm0 a t0pf tm0 p t0ae t0pe 20h emi tb1f time base 1 tb1e interrupt structure ht68f03/ht68f04 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 122 february 17, 2011 external interrupt the external interrupt is controlled by signal transitions on the int pin. an external interrupt request will take place when the external interrupt request flag, intf, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. to allow the program to branch to its re - spective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, inte, must first be set. additionally the correct inter - rupt edge type must be selected using the integ regis - ter to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-shared with i/o pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external inter - rupt request flag, intf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ reg- ister can also be used to disable the external interrupt function. comparator interrupt the comparator interrupt is controlled by the internal comparator. a comparator interrupt request will take place when the comparator interrupt request flag, cpf, is set, a situation that will occur when the comparator output changes state. to allow the program to branch to its respective interrupt vector address, the global inter - rupt enable bit, emi, and comparator interrupt enable bit, cpe, must first be set. when the interrupt is en - abled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. when the interrupt is serviced, the comparator interrupt request flag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within these devices there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, lvd interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an inter - rupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request flag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupts, namely the tm interrupts, lvd interrupt and eeprom interrupt will not be automatically reset and must be manually re - set by the application program. a/d converter interrupt some devices contain an a/d converter which has its own independent interrupt. the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request flag, adf, is set, which occurs when the a/d conversion pro- cess finishes. to allow the program to branch to its re- spective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must first be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d con - verter interrupt flag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the time base interrupts is to provide reg - ular time signal in the form of an internal interrupt. they are controlled by the overflow signals from their respec - tive timer functions. when these happens their respec - tive interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must first be set. when the interrupt is enabled, the stack is not full and the time base overflows, a subroutine call to their respective vector locations will take place. when the interrupt is ser - viced, the respective interrupt request flag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 123 february 17, 2011 the purpose of the time base interrupt is to provide an interrupt signal at fixed time periods. their clock sources origi - nate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is se - lected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. tbc register bit76543210 name tbon tbck tb11 tb10 lxtlp tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00110111 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10 : select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp : lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00 : select time base 0 time-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb ; = > ' ( & ? & ! # & ! # ! 7 # 5 1 4 ! 7 # 5 1 4 ! # % # ! # & ! # ! # ! # time base interrupt ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 124 february 17, 2011 eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def, is set, which occurs when an eeprom write or read cycle ends. to allow the program to branch to its respective interrupt vector address, the global inter - rupt enable bit, emi, eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and an eeprom write or read cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom in - terrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automat - ically cleared. as the def flag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector func - tion detects a low power supply voltage. to allow the program to branch to its respective interrupt vector ad- dress, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and a low voltage condi- tion occurs, a subroutine call to the multi-function inter- rupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automat - ically cleared. as the lvf flag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard type tms have two inter - rupts each, while the enhanced type tm has three in - terrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and standard type tms there are two interrupt request flags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced type tm there are three interrupt re - quest flags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request flags are set, a situa - tion which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, re - spective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must first be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subrou - tine call to the relevant multi-function interrupt vector lo - cations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to dis - able other interrupts, however only the related mfnf flag will be automatically cleared. as the tm interrupt re - quest flags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capability of wak - ing up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt re - quest flag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as ex - ternal edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be dis- abled then the corresponding interrupt request flag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 125 february 17, 2011 programming considerations by disabling the relevant interrupt enable bits, a re - quested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will re - main in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control se - quence will be damaged once a call subroutine is exe - cuted in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request flag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are al - tered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 126 february 17, 2011 low voltage detector lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the sup - ply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be gener - ated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a cer - tain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit76543210 name lvdo lvden vlvd2 vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 00 000 bit 7~6 unimplemented, read as 0 bit 5 lvdo : lvd output flag 0: no low voltage detect 1: low voltage detect bit lvden : low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 vlvd2 ~ vlvd0 : select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.4v ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 127 february 17, 2011 lvd operation the low voltage detector function operates by compar - ing the power supply voltage, v dd , with a pre-specified voltage level stored in the lvdc register. this has a range of between 2.0v and 4.4v. when the power sup - ply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power sup - ply voltage condition. the low voltage detector func - tion is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage de - tector, a time delay t lvds should be allowed for the cir - cuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. the low voltage detector also has its own interrupt which is contained within one of the multi-function inter - rupts, providing an alternative means of low voltage de - tection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request flag will be set, causing an in - terrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage de - tector wake up function is not required then the lvf flag should be first set high before the device enters the sleep or idle mode. " lvd operation configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defined for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed/low speed system oscillator selection - f osc : 1. hxt + lirc 2. erc + lirc 3. hirc + lirc 4. hirc + lxt 2 wdt clock selection - f s : 1. f sub 2. f sys /4 3 hirc frequency selection: 1. 4mhz 2. 8mhz 3. 12mhz note: the f sub and the f tbc clock source are lxt or lirc selection by the f osc configuration option. reset pin options 4 pa7/res pin options: 1. res pin 2. i/o pin watchdog options 5 watchdog timer function: 1. enable 2. disable 6 clrwdt instructions selection: 1. 1 instructions 2. 2 instructions lvr options 7 lvr function: 1. enable 2. disable 8 lvr voltage selection: 1. 2.10v 2. 2.55v 3. 3.15v 4. 4.20v ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 128 february 17, 2011 application circuits ht66f03/ht66f04 note: * recommended component for added esd protection. ** recommended component in environments where power line noise is significant. ht68f03/ht68f04 note: * recommended component for added esd protection. ** recommended component in environments where power line noise is significant. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 129 february 17, 2011 " " " 1 & & ( * $ * & $ + & + @ * $ @ @ ( ( ? @ " " " 1 & ( * $ * & $ + & + @ * $ @ @ ( ( ? @ ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 130 february 17, 2011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 131 february 17, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 132 february 17, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrd [m] tabrdl [m] read table to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 133 february 17, 2011 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 134 february 17, 2011 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 135 february 17, 2011 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 136 february 17, 2011 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 137 february 17, 2011 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 138 february 17, 2011 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 139 february 17, 2011 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 140 february 17, 2011 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrd [m] read table to tblh and data memory description the program code addressed by the table pointer (tbhp and tblp) is moved to the speci - fied data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 141 february 17, 2011 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 142 february 17, 2011 package information 10-pin msop outline dimensions symbol dimensions in inch min. nom. max. a 0.043 a1 0.000 0.006 a2 0.030 0.033 0.037 b 0.007 0.011 c 0.010 d 0.118 e 0.193 e1 0.118 e 0.020 l 0.016 0.024 0.031 l1 0.037 0 8 symbol dimensions in mm min. nom. max. a 1.10 a1 0.00 0.15 a2 0.75 0.85 0.95 b 0.17 0.27 c 0.25 d 3.00 e 4.90 e1 3.00 e 0.50 l 0.40 0.60 0.80 l1 0.95 0 8 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 143 february 17, 2011 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c 0.386 0.394 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c 9.80 10.01 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25 0 8 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 144 february 17, 2011 product tape and reel specifications reel dimensions sop 16n (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 145 february 17, 2011 carrier tape dimensions sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 146 february 17, 2011 ! " # $ % & $ ' # ( ) $ ) * + , - + . - / $ , - . % $ * . ) + / $ 0 / ( * - . - ht66f03/ht66f04/ht68f03/ht68f04 rev. 1.30 147 february 17, 2011 copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com |
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